1.1.1 Structure and function of the processor

Question 1

Memory Address Register (MAR)

Answer 1

Small memory location inside the CPU to assist with FDE cycle. Holds the address of the memory locations that the processor will read/write data to

Question 2

Program Counter (PC)

Answer 2

Small memory location inside the CPU to assist with the fetch-execute cycle. Holds the address of the next instruction to be executed. When the FDE cycle is completed it increments by one

Question 3

Register

Answer 3

Small, fast memory located in the CPU. Designed for a specific purpose, where data or control information is stored temporarily to enable the FDE cycle to operate

Question 4

Von Neumann Architecture

Answer 4

Instructions and data share the same memory space. Instructions are fetched, decoded and executed one at a time. One system bus. Uses a stored program concept

Question 5

Pipelining

Answer 5

While the current instruction is being executed, the next is being decoded and the one after that