.131 WK 4-6

Question 1

Define ISA

Answer 1

interface between hardware + software - set of commands a processor can understand/execute

Question 2

ALU provides…

Answer 2

registers (store operands + results), status flags (overflow, zero or negative)

Question 3

ALU implements

Answer 3

arithmetic + logic operations

Question 4

How to add 2 bits?

Answer 4

half adder aka S = A XOR B and S = A . B

Question 5

How to add 3 bits?

Answer 5

full adder aka S = Cin XOR (A XOR B) Cout = A.B + Cin . (A XOR B)

Question 6

What is the problem with ripple-carry adders and how to solve this?

Answer 6

slow as each stage has to wait for carry bit from above
can solve with carry select adders

Question 7

How does a carry select adder work?

Answer 7

split problem by adding lower n/2 bits as usual but add upper n/2 bits using 2 full adders where one Cin is 1 and the other 0

Question 8

Benefit of a carry select adder?

Answer 8

effectively doubles the speed - can keep splitting as long as cost/space allows

Question 9

What is a status flag?

Answer 9

bits organised into a special register called the flags register - can be zero, negative or overflow

Question 10

How does an ALU identify an overflow?

Answer 10

inputs’ sign bits are the same but the result has a different sign
Cin ⊕ Cout = 1 = arithmetic overflow error

Question 11

How does the ALU perform simple multiplication + division?

Answer 11

Can be done with repetitive adders (slow)
Bit shifting (only works for powers of 2)

Question 12

How does bit shifting work?

Answer 12

shifts number to left(multiply)/right(divide) by n^2
e.g shift left by 1 = x 2
shifts may be arithmetic, logical, rotate or rotate through carry

Question 13

What are the types of volatile memory?

Answer 13

dynamic and static

Question 14

Dynamic volatile memory is…

Answer 14

used for main memory
slower but cheaper than static

Question 15

Static volatile memory is…

Answer 15

used for registers + caches
fast so relatively expensive

Question 16

Main memory

Answer 16

each location holds 1 unit of info
identified by address (usually linear 0..n) which typically maps to multiple memory chips - address decoder maps linear addresses to specific location in a specific memory chip

Question 17

What ways can machine architecture organise mutli-byte words in memory?

Answer 17

big-endian - location (byte) with the lowest memory address holds the most significant byte
little-endiain - location with the lowest memory address holds the least-significant byte

Question 18

What does big-endian mean?

Answer 18

multi-byte words are organised so the location with the lowest memory address holds the most-significant byte

Question 19

What does little-endian mean?

Answer 19

multi-byte words are organised so the location with the lowest memory address holds the least-significant byte

Question 20

How does static memory store bits

Answer 20

stored bits are organised into multi-bit storage slots called registers
use networks of logic components (NAND gates) to build storage for individual data bits

Question 21

What does combinatorial logic entail?

Answer 21

outputs are purely a function of its inputs

Question 22

What does sequential logic entail?

Answer 22

its outputs are a function of its inputs AND its current outputs
involves feedback of the outputs to the inputs which is the hook on which we hang memory

Question 23

set-reset (S-R) flip-flop

Answer 23

remembers its current state where Q0 = current + Q = next
high pulse on S -> Q=1(set)
high pulse on R -> Q=0 (reset)
(both S and R can’t be 1)

Question 24

Limitations of S-R flip-flop

Answer 24

• has distinct set + reset inputs rather than a single input (could set state if 1 and reset if 0)
• no way of telling the f-f exactly when it should store input data (would like a latch signal to supervise)

Question 25

Clocked D-type flip-flop

Answer 25

D = 1, L = 1 → Q = 1 Q0 = 1 but D = 0, L= 0 → Q = 1 Change D = 0 to set latch to 0

Question 26

D-type flip-flop limitation

Answer 26

need output enable to have closer control of when existing data leaves + new data arrives

Question 27

Master-slave flip-flop

Answer 27

slave is only readable where output enable is high pulse if master latch = high → data signal is stored in master but slave is untouched if master latch = low → data moves to slave can implement registers using multiple master-slave flip-flops

Question 28

What is a bus?

Answer 28

bundles of wires that connect elements of VN architecture one wire per bit

Question 29

What do the different buses do?

Answer 29

address bus - runs between CU and main memory to tell memory to access a specific address data bus - runs between CU and main memory to send data control bus some processors may have internal + external buses (external may be narrower to reduce external pins + therefore cost)

Question 30

What is bus width?

Answer 30

number of bits that can be read/written to/from memory at once for data bus amount of addressable memory for address bus

Question 31

Why do buses need output enable?

Answer 31

bus wires are shared so we must ensure there is only one active output at a given time

Question 32

Control Unit

Answer 32

“little program” running inside the processor that endlessly executes the fetch-decode cycle - controls sequences + other architectural modules using their respective control lines (e.g latch, output enable, function select, carry + shift L/R) CU is driven by clock ticks/pulses

Question 33

How can CU fetch-ex loops be implemented?

Answer 33

as a FSM (hard-wired sequential logic - built directly in terms or NAND gates) OR as microcode (sequence of micro-instructions in a micro-memory)

Question 34

What are the pros + cons of each CU fetch-ex loop implementation?

Answer 34

FSM - high performance but expensive + hard to evolve microcode - more flexible but slightly lower performance

Question 35

What is pipelining?

Answer 35

exploit inherent parallelism inside CU to speed up fetch-ex cycle if split cycle into n-stages → get n x speedup

Question 36

What are the hazards associated with pipelining?

Answer 36

- control hazards: occur when a control-transfer instruc. changes the flow of execution - data hazards: occur when instruc. n depends on a result from previous instruc. or when two parts of the pipeline need access to the same data - structural hazards: occur when two parts of the pipeline need access to the same piece of hardware

Question 37

What happens when we encounter a pipeline hazard?

Answer 37

may cause pipeline to “stall” so we must “flush” it to continue might considerably reduce speedup

Question 38

I/O devices

Answer 38

- input = keyboard, mouse, track ball, touch screen, camera, environmental sensor - output = display, printer, speaker, environmental actuator - input + output = network interfaces (ethernet, wifi, bluetooth, etc.), disks, audio cards, MIDI devices

Question 39

The I/O system enables...

Answer 39

attachment of I/O devices to the processor

Question 40

Challenges of I/O device connection

Answer 40

- speed-gap challenge: I/O devices are often mechanical so run orders of magnitude slower than the CPU - device diversity challenge: differences like data-access modes (read-only/write-only/read-and-write, access by individual byte/block and access randomly/sequentially), device specific operations + I/O protocols

Question 41

What is a device driver?

Answer 41

software plug-ins inside the OS that abstract over device diversity by grouping sets of similar types of devices

Question 42

What do device drivers do?

Answer 42

- register device with the OS + initialising it - initiate data transfers to/from a device - monitor status events from a device - manage device/system shutdowns so OS doesn’t stop till all unwritten data is stored + device is left in a safe state

Question 43

Two-fold classification (types) of device + device driver

Answer 43

character devices - send + receive 1 byte at a time - e.g. keyboard block devices - send + receive multi-byte block at a time - e.g. hard disk

Question 44

Two-fold classification of processor support for I/O

Answer 44

isolated I/O - processor provides dedicated physical pins for the connection of I/O devices + dedicated instructions for I/O operations memory-mapped I/O = devices sit within the CPU’s linear memory address space

Question 45

Pros + cons of memory-mapped I/O classification

Answer 45

simple, flexible programming model but adds complexity to devices - need to understand larger addresses to work at memory speeds

Question 46

Pros + cons of isolated I/O classification

Answer 46

suited to simple devices though having fixed set of special I/O instruc. doesn't help w/ device diversity

Question 47

What is an example of isolated I/O classification?

Answer 47

Intel x86 instructions - dedicated IN + OUT - port addresses are typically 8 bits (narrower than main memory addresses)