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Microprocessors > End of Chapter Summaries > Flashcards

End of Chapter Summaries Flashcards

1
Q

What are the three types of unconditional jump instructions?

A

short, near, far, wherever you are

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2
Q

allows a branch to within +127 and -128 bytes

A

Short Jump

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3
Q

allows a jump to any location in the current code segment

A

Near Jump

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4
Q

allows a jump to any location in the memory system

A

Far Jump

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5
Q

Whenever a label appears with a JMP instruction or conditional jump, the label, must be followed by a ______

A

Colon

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6
Q

The _____ that follows a short or near jump is the distance from the next instruction to the jump location.

A

Displacement

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7
Q

jump to the location stored in a memory word

A

Near Indirect Jump

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8
Q

jump to the location stored in a memory doubleword

A

Far Indirect Jump

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9
Q

Are all short jumps that test one or more of the flag bits

A

Conditional Jumps

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10
Q

A special conditional jump instruction that decrements CX and jumps to the label when CX is not 0.

A

LOOP

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11
Q

The _______ instruction jumps if CX is not 0 and if an equal condition exists.

A

LOOPE

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12
Q

The _______ instruction jumps if CX is not 0 and if an not equal condition exists.

A

LOOPNE

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13
Q

are groups of instructions that perform one task and are used from any point in the program.

A

Procedureq

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14
Q

instruction that links to a procedure

A

CALL

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14
Q

instruction that returns from a procedure

A

RET

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15
Q

directive that defined the name and type of procedure

A

PROC

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16
Q

declares the end of the procedure

A

ENDP

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17
Q

is a combination of a PUSH and a JMP instruction

A

CALL

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18
Q

places the contents of IP on the stack

A

Near CALL

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19
Q

places both IP and CS on the stack

A

Far CALL

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20
Q

removes the return address from the stack and placing it into IP

A

Near Return

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21
Q

removes the return address from the stack and placing it into IP and CS

A

Far Return

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22
Q

are either software instructions similar to CALL or hardware signals used to call procedures

A

Interrupts

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23
Q

returns control to the interrupted software

A

IRET

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24
Q

How many interrupt vectors exist in the first 1KB of memory?

A

256 interrupt vectors

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25
Q

How many interrupt vectors are defined by Intel?

A

32

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26
Q

How many interrupt vectors are user interrupts?

A

224

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27
Q

must be used to return from an interrupt service procedure

A

IRET

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28
Q

a conditional interrupt that calls an interrupt service procedure if the overflow flag is 1

A

INTO

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29
Q

tests the condition of the BUSY or TEST pin on the microprocessor

A

WAIT

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30
Q

passes instruction to the numeric coprocessor

A

ESC

31
Q

compares the contents of any 16 bit register against the contents of two words of memory

A

BOUND

32
Q

holds local memory variables for the procedure

A

stack frame

33
Q

creates the stack frame

A

ENTER

34
Q

removes the stack frame from the stack

A

LEAVE

35
Q

The ____ clock generator provides the system clock (CLK), READY synchronization, and RESET synchronization

A

8284A

36
Q

is used by the microprocessor to send the address to the memory or I/O and the ALE signal to the demultiplexers

A

T1

37
Q

is used to send data to memory for a write and to test the READY pin and activate control signals RD or WR

A

T2

38
Q

allows the memory time to access data and allows data to be transferred between the microprocessor and the memory or I/O

A

T3

39
Q

is where data are written

A

T4

40
Q

A bus cycle that consists of ___ clocking periods act as the basic system timing.

A

4

41
Q

Stretch the bus cycle by one or more clocking periods to allow the memory and I/O additional access time.

A

Wait states (Tw)

42
Q

How many combinations can 10 address pins have?

A

1024

43
Q

is programmed by an EPROM programmer and can be erased if exposed to ultraviolet light

A

EPROM

44
Q

is programmed in the system by using a 12 V or 5.0 V programming pulse.

A

Flash Memory (EEPROM)

45
Q

retains data for as long as the system power supply is attached.

A

Static RAM (SRAM)

46
Q

retains data for only a short period, usually 2–4 ms.

A

Dynamic RAM (DRAM)

47
Q

3-to-8 line decoder

A

74LS138

48
Q

2-to-4 line decoder

A

74LS139

49
Q

The ______ address decoder for microprocessors like the 8088 through the Pentium 4 reduce
the number of integrated circuits required to complete a functioning memory system.

A

PLD

50
Q

Many EPROMs available today have an access time of _______, which is too slow for the 5 MHz 8088. In order to circumvent this problem, a wait state is inserted to increase
memory access time to _______.

A

450 ns, 660 ns

51
Q

________ features are also available for memory systems, but these require the storage of many more bits.

A

Error-correction

52
Q

The __________ of memory is enabled by the BHE control signal

A

High Bank

53
Q

The __________ of memory is enabled by the A0 address signal or by the BLE control signal

A

Low Bank

54
Q

The 8086–Core2 microprocessors have two basic types of I/O instructions:

A

IN and OUT

55
Q

inputs data from an external I/O device into either the AL (8-bit) or AX (16-bit) register

A

IN

56
Q

outputs data from AL or AX to an external I/O device and is available as a fixed, variable, or string instruction.

A

OUT

57
Q

sometimes called direct I/O

A

Isolated I/O

58
Q

uses a separate map for the I/O space, freeing the entire memory for use by the program.

A

Isolated I/O

59
Q

uses a portion of the memory space for I/O transfers

A

Memory-mapped I/O

60
Q

is either built into a programmable peripheral or located separately.

A

Buffer

61
Q

All input devices are ______ so that the I/O data are connected only to the data bus during the execution of the IN instruction.

A

buffered

62
Q

All output devices use a _____ to capture output data during the execution of the OUT
instruction

A

latch

63
Q

is the act of two independent devices synchronizing with a few
control lines.

A

Handshaking or Polling

64
Q

are required for most switch-based input devices and for most output devices that are not TTL-compatible

A

Interfaces

65
Q

decodes only a l6-bit address for variable port instructions and often an 8-bit port number for fixed I/O instructions

A

I/O port decoder

66
Q

decodes the entire address

A

Memory Address Decoder

67
Q

is a programmable peripheral interface (PPI) that has 24 I/O pins that are programmable in two groups of 12 pins each (group A and group B).

A

82C55

68
Q

Mode 0 of 82C55

A

Simple I/O

69
Q

Mode 1 of 82C55

A

Strobed I/O

70
Q

Mode 2 of 82C55

A

Bidirectional I/O

71
Q

The ________ device requires a fair amount of software, but it displays ASCII-coded
information

A

LCD Display

72
Q

The ______ is a programmable interval timer that contains three l6-bit counters that count in binary or binary-coded decimal (BCD)

A

8254

73
Q

Modes of 8254

A

0 - Events Counter
1 - retriggerable, monostable multivibrator
2 - pulse generator
3 - square-wave generator
4 - software-triggered pulse generator
5 - hardware-triggered pulse generator

74
Q

The _______ is a programmable communications interface, capable of receiving and transmitting
asynchronous serial data

A

16550

75
Q

The ________ is an 8-bit digital-to-analog converter that converts a digital signal to an analog
voltage within 1.0 μs

A

DAC0830

76
Q

The _______ is an 8-bit analog-to-digital converter that converts an analog signal into a
digital signal within 100 μs.

A

ADC0804

Microprocessors (28 decks)

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