Chapter 9 Pin Functions Flashcards

1
Q

are connected to the status output pins on the 8086/8088 microprocessor

A

Status Inputs (S2, S1, S0)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
2
Q

provides internal timing and must be connected to the CLK output pin of the 8284A clock generator.

A

Clock Input (CLK)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
3
Q

is used to demultiplex the address/data bus.

A

Address Latch Enable (ALE)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
4
Q

controls the bidirectional data bus buffers in the system

A

Data Bus Enable (DEN)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
5
Q

is output by the 8288 to control the direction of the bidirectional data bus buffers.

A

Data Transmit/Receive (DT/R)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
6
Q

causes the 8288 to enable the memory control signals.

A

Address Enable (AEN)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
7
Q

enables the command output pins on the 8288

A

Control Enable (CEN)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
8
Q

selects either the I/O bus mode or system bus mode operation.

A

I/O bus mode (IOB)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
9
Q

is a command output used to provide I/O with an advanced I/O write control signal.

A

Advanced Input/Output Write Command (AIOWC)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
10
Q

provides I/O with its read control signal.

A

IORC

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
11
Q

provides I/O with its main write signal.

A

IOWC

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
12
Q

provides memory with an early
or advanced write signal.

A

Advanced Memory Write (AMWT)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
13
Q

provides memory with its normal write control signal.

A

MWTC

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
14
Q

provides memory with a read control signal

A

MRDC

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
15
Q

acknowledges an interrupt request
input applied to the INTR pin

A

INTA

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
16
Q

selects cascade operation for an interrupt controller if IOB is grounded, and enables the I/O bus transceivers if IOB is tied high.

A

Master Cascade/Peripheral Data (MCE/PDEN)