3

Question 1

Overlapped capacitance

Answer 1

Due to gate region ontop of gate and p type doping region

Question 2

Capacitance between source and drain is in series with source and gate and gate and drain capacitance.

Question 3

Why is speed determined on capacitance

Answer 3

Tau = r c

Question 4

Use capital letter for subscripts for DC and lowercase for lowercase subscripts.

Question 5

What is the unit of Cox?

Answer 5

F/ m^2

Question 6

Cox remains the same for pmos and cmos while width changes

Question 7

In saturation region, the tapered region adds more conductor to the source side do the Cgs is greater than Cgd

Question 8

Gate capacitance is composed of

Answer 8

Cgs + Cgd + Cgb

Question 9

There is a rise and fall time in voltage from logic 0 to logic 1 and vice versa.

Question 10

Time it takes for signal to go from 10% to 90% for rise delay.

Answer 10

I.e 0.1 to 0.9 V for 0-1V

Question 11

Propagation delay

Answer 11

Maximum time that digital logic circuit takes to respond and reach 50% of transition voltage input ton50% of voltage output.

Question 12

Contamination delay

Answer 12

Minimum delay for a signal to propogate from input to output.

Question 13

Noise margin low = Nml

Answer 13

V_il - V_ol

Question 14

Noise margin high = N_mh

Answer 14

V_oh - V_ih