3. Machine Level Architecture

Question 1

What is Main memory

Answer 1

All data and instructions stored in main memory

Question 2

Define processor

Answer 2

Executes programs and supervises the operation of the rest of the system

Question 3

Define main memory

Answer 3

Data store that can be directly addressed by the CPU

Question 4

Define RAM

Answer 4

Random access memory Can be read from and written to. Data is cleared when the power is off

Question 5

Define ROM

Answer 5

Read-only memory Can only be read from. Data is maintained when the power is off

Question 6

What is in the 3 box model

Answer 6

CPU, Main memory, Input/ Output System bus

Question 7

What is the system bus

Answer 7

The Control Bus The Address Bus The Data bus

Question 8

Define address bus

Answer 8

Single directional Carries address signals from the CPU to Main Memory and I/O devices

Question 9

Define Data Bus

Answer 9

Bi- directional Bus Typically consists of 32 wires Used to transport data between the 3 components

Question 10

What is the benefit of a larger data bus

Answer 10

The larger the data bus, the more data can be transported at one time. Therefore more complex instructions can be used

Question 11

Define Control Bus

Answer 11

Bi-directional bus Typically consists of 8 wires. Used to transport control signals between the 3 components.

Question 12

Define Computer Bus

Answer 12

A set of parallel wires connecting independent components of a computer system

Question 13

Define I/O

Answer 13

Input / Output Allows the CPU to communicate with peripherals

Question 14

Define Input Devices

Answer 14

Used to get information into the system - keyboard, mouse, touch screen

Question 15

Used to send information out of the system -VDU( Visual Display Unit), printer, speakers

Answer 15

Define Output Devices

Question 16

Define I/O controller

Answer 16

An electronic circuit that connects to a system bus and an I/O device. It provides the correct voltages and currents for the system bus and the I/O device . Keyboard controller, disk controller, video display controller

Question 17

Define I/O device

Answer 17

A hardware unit that sends or receives data, or stores data by communicating with the processor and main memory through an I/O controller

Question 18

Define Periperal

Answer 18

A computer device that is not part of the CPU. Can be external - Mouse, Keyboard, Monitor Can be internal - CD drive

Question 19

Define I/O port

Answer 19

A set of data, command and and status registers. Allows for I/O devices to be connected without the need for special equipment

Question 20

Define secondary storage

Answer 20

Permanent storage memory not directly connected to the processor

Question 21

Define Addressable memory

Answer 21

Data blocks in main memory

Question 22

Define Stored Program Concept

Answer 22

A program must be in Main Memory to be executed. It is processed with fetch, decode, execute one at a time

Question 23

Define ALU

Answer 23

Arithmetic Logic Unit Does operations such as ADD, SUBTRACT. Performs the arithmetic and logic operations.

Question 24

Define Program Control Unit

Answer 24

Fetches program instructions from memory, decodes them and executes them, 1 at a time

Question 25

Define Registers

Answer 25

Fast memory locations inside the processor that may be dedicated or general purpose

Question 26

Define Clock

Answer 26

A timing device connected to the processor that synchronises the fetch, decode, execute cycle.

Question 27

Define Clock speed

Answer 27

The number of cycles performed by the CPU per second. Measured in hertz.

Question 28

What are the 4 registers used in the fetch, decode execute cycle

Answer 28

Program counter Memory address register Memory buffer register Current instruction register

Question 29

Define Program Counter

Answer 29

An incrementing counter that keeps track of the memory address of which instruction is next

Question 30

Define Memory Address Register

Answer 30

Holds the address in memory of the next instruction to be executed

Question 31

Define Memory Buffer Register

Answer 31

A two-way register that holds the data fetched from memory or data waiting to be stored in memory

Question 32

Define Current Instruction Register

Answer 32

A temporary holding ground for the instruction that has just been fetched from memory

Question 33

Define General Purpose Register

Answer 33

A register not assigned a specific role. Programmers may use general purpose registers

Question 34

Define dedicated register

Answer 34

A register assigned a specific role. Programmers may use some, but not all dedicated registers

Question 35

How can you increase performance

Answer 35

Increase clock speed Adjust word length Increase bus width

Question 36

Why must clock speed be limited

Answer 36

Heat generated in the chip by higher frequencies can't be removed quickly enough

Question 37

Define Word Size

Answer 37

The number of bits of information that a processor can process at one time

Question 38

Define Bus Size

Answer 38

The number of bits of information a bus can carry at one time The u umber of wires making up the bus

Question 39

Define Machine Code

Answer 39

Simple instructions that are executed directly by the CPU Binary code

Question 40

Define Instruction Set

Answer 40

The range of instructions that a CPU can execute

Question 41

Define EEPROM

Answer 41

Electronically erasable programmable read-only memory. Its contents may be altered but writing is about 100 times slower than reading

Question 42

Define System Bus

Answer 42

The main highway connecting the processor, main memory and I/O controllers

Question 43

What are the 2 parts of an instruction

Answer 43

OPCODE OPERAND

Question 44

Define OPCODE

Answer 44

The instruction name / operation

Question 45

Define OPERAND

Answer 45

The data or address to perform the instruction on

Question 46

First step of Fetch Execute cycle

Answer 46

MAR ← [PC] The contents of the Program Counter, the address of the next instruction to be executed is placed in the Memory Address Register

Question 47

Second Step of the Fetch Execute Cycle

Answer 47

MBR ← [Memory Addressed] PC ← [PC + 1] The Address is sent from the MAR, along the Address Bus to Mian Memory. The Instruction at the adderss is returned along the Data Bus to the Memory Buffer Register. Simultainiously, the Conents of the Program Counter is increased by 1

Question 48

Third Step of the Fetch Execute Cycle

Answer 48

CIR ← [MBR] The MBR loads the Current Instruction Register with the instruction to be executed

Question 49

Fourth step of the Fetch Execute Cycle

Answer 49

Decode Instruction

Question 50

Fifth step of the Fetch Execute Cycle

Answer 50

Execute Instruction Uses registers such as ALU if necessary