5. Logic Design

Question 1

Why do we use binary (on/off) as opposed to ternary (full, half, off)?

Answer 1

The computer could misread a shift from off to full as a half state.

Question 2

What is meant by a combinational logic circuit?

Answer 2

A circuit whose output only depends on the current inputs.

Question 3

What is meant by a sequential logic circuit?

Answer 3

A circuit whose outputs depends on the current inputs and previous inputs (requires memory).

Question 4

Give three examples of minimally functionally complete gates.

Answer 4

Any from:
{AND, NOT}
{OR, NOT}
{NAND}
{NOR}

Question 5

A multiplexer takes in three inputs, a, b and S.
When S is on, value a is outputted. When S is off, value b is outputted.

What is the simplified combinational circuit for a multiplexer?

Answer 5

a.S + b.{not S}

Question 6

Construct a 1 bit adder for an arithmetic n-bit adder.

Answer 6

The adder requires three inputs (a,b and a carry c) and two outputs (the sum s and the output carry o).

Then, considering the sum and carry independently,

s = ~a.~b.~c + ~a.b.~c + a.~b.~c + a.b.c
c = b.c + a.c + a.b

Question 7

Explain how a ripple carry adder is formed, stating the minimum total gate time for an 8-bit adder.

Answer 7

A ripple carry adder is made up of a set of 1-bit adders.

Minimum adder is:
bit 1 is half-adder: 2 gates
bit 2-7 is full adders: 3 gates * 6 = 18 gates
bit 8 is adder (but no carry) : 2 gates.

Thus, total is 22 gates.

Question 8

What affects the propagation delay?

Answer 8

The technology, delay through each gate and number of gates driven by a gate’s output.

Question 9

If there are n feedback signals in a sequential logic circuit, how many states are there possible?

Answer 9

2ⁿ states

Question 10

A sequential circuit with an original input and a feedback input OR’ed together has what function?

Answer 10

Outputs 1 if there has ever been a 1 given to the circuit.

Question 11

In a NOR SR-latch, what happens when IN1 has the following sequence of bits passed to it: 0110?

[Assume IN1, IN2 and OUT2 are 0 to begin]

Answer 11

0: No change
1: OUT1 -> 0, OUT2 -> 1
1: No change
0: No change

Question 12

In a NOR SR-latch, with a reset, set and outputs Q and ~Q, what does setting the reset line to 1 do?

Answer 12

Setting the reset line sets Q to be 0 (likewise the set line sets it to 1)

Question 13

Give an example of a circuit that causes a glitch due to asynchronicity.

Answer 13

(~~~a).a

To begin, a is 0, so ~~~a is 1. When a 1 signal is sent in, a becomes 1, and so the output is 1. Then, the ~~~a becomes 0 and it quickly flicks back to 0.

Question 14

How are glitches prevented in a SR-latch?

Answer 14

A clock is added (set of ands between the dividing ‘NOT’ and the latch itself).

Question 15

State the common name for a clocked SR latch?

Answer 15

D flip-flop

Question 16

Compare the level-triggered D flip-flop and edge-triggered D flip-flop.

Answer 16

The level-triggered D flip-flop has D propagated to Q when the clock is 1.

The edge-triggered D flip-flop has D propagated to Q on a positive clock edge.

Question 17

How are registers created in logic?

Answer 17

Multiple D flip-flops together using a common clock.

Question 18

What is the process for implementing an FSM?

Answer 18

• Choose encoding for states (e.g S0 = 00, …, )
• Build truth table for next state s1’, s0’ and output z
• Generate logic equations for s1’, s0’ and z.
• Design combination logic from logic equations and add state-holding register.