All cards

Question 1

Propagation delay

Answer 1

Time between the input changing and the output responding.

Behaves as you would expect

Question 2

Inertial delay

Answer 2

Exists due to capacitances in the gates. Similar to propagation delay, but if pulses are too small (shorter than the inertial delay) then the output will not respond to it

Question 3

Transport delay

Answer 3

Time taken for a signal to propagate along a wire.

0 for an ASIC but matters for PCBs etc

Question 4

Verilog ‘net’

Answer 4

Connect things together, like wires in am actual circuit

Question 5

Verilog ‘registers’

Answer 5

Hold information. ‘Variable’ data type

Question 6

Verilog ‘wires’

Answer 6

Default for ports. They take the value from the circuit driving them, but don’t store it. Like a multimeter in a circuit. ‘Net’ data type

Question 7

Verilog ‘integers’

Answer 7

Used for numerical stuff. -ves are done using 2’s complement

Question 8

Logic synthesis

Answer 8

Going from a behavioural model of how you want a system to behave, to an actual implementation of that system

Question 9

Dataflow models

Answer 9

Models a combinational logic system as data with operations performed on it. Are synchronous

Question 10

Register Transfer Level (RTL) dataflow model

Answer 10

A dataflow model that focuses on operations performed on data as it goes between registers

Question 11

Transparent latch

Answer 11

A module with 2 inputs - 1 data in, 1 input boolean. The output will either equal the data in or maintain its current state, depending on the input boolean

Question 12

Combinational behaviour

Answer 12

Output is ONLY a function of the present inputs (no memory)

Question 13

Sequential behaviour

Answer 13

Output is a function of present AND past inputs (has memory)

Question 14

Verilog ‘initial’ block

Answer 14

Runs once, never repeats. Similar to a setup loop. Single pass behaviour

Question 15

Verilog ‘always’

Answer 15

Cyclic behaviour - can execute many times. Executes when there is an ‘event’ (change to a variable) on its sensitivity list

Question 16

Blocking assignment

Answer 16

Evaluated and assigned in a single step. Execution flow in the procedure is ‘blocked’. Statement must be executed before further statements can execute

Question 17

Non-blocking assignment

Answer 17

2 stage - RHS processed immediately but assignment is delayed. Waits until other evaluations in the current time step have been done. Flow is not blocked. Outcome is independent of the ordering of statements

Question 18

Instruction Set Architecture (ISA)

Answer 18

The set of instructions (in assembly code) that a system can perform (e.g. ADD, MOV etc)

Question 19

Arithmetic Logic Unit (ALU)

Answer 19

Made up of an arithmetic part and a logic part, with select lines to choose one. Receives DATA from memory or registers

Question 20

Control Unit (CU)

Answer 20

Controls the interpretation of instructions (e.g. fetching operands). Fetches machine language INSTRUCTIONS from memory and decodes them

Question 21

Von Neumann Architecture

Answer 21

Has a single memory interface used for both code and data. It is up to the programmer to make sure that the interpretation is correct

Question 22

Harvard Architecture

Answer 22

Has 2 separate memory interfaces for data and code

Question 23

Tristate buffer

Answer 23

3 output states - high, low or high-Z

Question 24

Why is the (Memory) Address Register required if there is already a Program Counter

Answer 24

The AR can be used for holding both instructions and data- the AR is a convenient place to store the data. Also, latching the address of instructions in the AR means that the PC can be incremented at the same time as an instruction fetch

Question 25

Why are bi-directional buffers needed to connect the data bus to memory chips?

Answer 25

Data goes between the CPU and memory via the bus. When writing to memory: The buffers are needed to drive the memory because the CPU does not have the capacity to drive them on its own. The buffers are placed on the bus rather than the CPU itself because of power consumption limitations. When reading from memory: The bus is noisy, so Schmitt triggers are used

Question 26

Why is the Instruction Register necessary

Answer 26

It provides the input to the FSM, and this value needs to be consistent. The FSM output goes to the control path, so if the input to the FSM changed then operation would be unpredictable

Question 27

Why does the Program Counter need access to the internal data bus?

Answer 27

In order to carry out jump instructions - a value has to be loaded in

Question 28

Microcode

Answer 28

A sequence of hardware-level control words, used to implement higher-level machine code instructions. The microcode sequences are held in ROM, which is connected to control inputs of the CPU's internal components.

Question 29

Hardwired control

Answer 29

Instructions are implemented in hardware - e.g. a block of multipliers and adders to make up an instruction. An FSM picks between the blocks of logic to use, based on the op-code.

Question 30

Give the benefits and disadvantages of microcode vs hardwired control

Answer 30

Hardwired control is faster, but it is in hardware so can only be changed by changing the hardware. It is better for RISC processors as there are fewer instructions. Microcode is easier to design and modify and is much better for complex instructions. But it is slower so it can be less efficient if complex instructions are rarely used.

Question 31

Restoring division

Answer 31

'restores' the dividend to its previous (+ve) value when dividend - divisor is -ve

Question 32

Non-restoring division

Answer 32

Does not restore the dividend if it becomes -ve

Question 33

Program counter (PC)

Answer 33

Special register which stores the ADDRESS of the next instruction to be fetched

Question 34

Big endian

Answer 34

The most significant byte (not bit). Is put at the byte with the lowest adress

Question 35

Immediate addressing

Answer 35

The operand is a constant given in the instruction itself

Question 36

Base/displacement addressing

Answer 36

Operand is in a memory location, the address of which is the value found in a register plus a constant

Question 37

PC relative addressing

Answer 37

The value in the immediate field (of the instruction itself) gives an offset. This is added to the next PC value to give the address of the instruction to be fetched.

Question 38

Implied addressing mode (as determined by the bits in the instruction)

Answer 38

The operand is implied by the instruction. The instruction makes it obvious what the operand must be

Question 39

Immediate addressing mode (as determined by the bits in the instruction)

Answer 39

The operand IS the data given in the instruction

Question 40

Register addressing mode (as determined by the bits in the instruction)

Answer 40

Data can be found in a register in the processor

Question 41

Memory addressing mode (as determined by the bits in the instruction)

Answer 41

Operands are stored in memory

Question 42

Advantages and disadvantages of immediate addressing

Answer 42

+ Data can be fetched at the same time as the instruction + No need for a memory reference + Fast - Only a constant can be supplied this way - Value of the constant must be small enough to fit in the field

Question 43

Advantages and disadvantages of register addressing

Answer 43

+ Only needs a small address field (of the instruction) + Shorter instructions are possible + No memory access required - fast + Good for frequently accessed variables - There aren't that many registers available - Limited address space is available

Question 44

Advantages and disadvantages of direct memory addressing

Answer 44

+ only takes one memory access to get the data + No calculations are required to find the address + Fast for global variables - Address of global variables must be known when program is compiled - Limited address space is available

Question 45

Flow control instructions

Answer 45

``` Change the contents of the PC Come in 3 types: - HALT - JUMP - CALL ```

Question 46

JUMP flow control instruction

Answer 46

A straightforward change of the PC contents. Can be conditional or unconditional.

Question 47

CALL flow control instruction

Answer 47

Remembers the address of the next instruction (that would've been processed if the call hadn't happened), does the stuff associated with the call then returns to the point in the program where it left off. Used for subroutines.

Question 48

What is in the stack frame

Answer 48

- Return address - Passed parameters - Local variables - Returned variables

Question 49

Instruction Register (IR)

Answer 49

Holds instructions over multiple cycles. Holds the address of data (operands)

Question 50

Temporal locality principle

Answer 50

A location that has been accessed recently is likely to be accessed again soon

Question 51

Spatial locality principle

Answer 51

If a location has been accessed, the next location that must be accessed is likely to be nearby

Question 52

Cache line

Answer 52

The chunk of data that is transferred from memory to the cache in one go (shelf of books analogy)

Question 53

Content Addressable Memory (CAM)

Answer 53

The data stored in memory is made up of the data itself and a tag. When searching the cache, the tag is checked to see if the cache entry holds the required data. If the data is there, there is a hit. Used in cache memory systems

Question 54

Direct mapped cache

Answer 54

Each block in main memory is mapped to a single cache location - each block can ONLY go to that location.

Question 55

Give the benefits and disadvantages of a direct mapped cache

Answer 55

+ Simple, easy to implement - Shitty performance - If multiple memory blocks that use the same bit of cache keep being used, that part of the cache has to keep being cleared - Lots of cache misses

Question 56

Fully associative cache

Answer 56

Each block of memory is mapped to ANY cache location

Question 57

Give the benefits and disadvantages of a fully associative cache

Answer 57

+ Best performance + lots of flexibility - Harder to implement - You need to know the full address in order to locate a block (since the data could be anywhere)

Question 58

Set associative cache

Answer 58

Compromise between fully associative cache and direct mapped cache. Cache is split into sets that data from certain blocks of memory can access. Within a set, it is fully associative

Question 59

Give the benefits and disadvantages of a set associative cache

Answer 59

- Can occasionally suffer similar drawbacks as direct mapped + Hardware fairly simple + Don't have to search through the whole cache + You get the best of both worlds + You rock out the show

Question 60

IIR filter

Answer 60

Infinite Impulse Response filter

Question 61

FIR filter

Answer 61

Finite Impulse Response filter

Question 62

Recursive filter

Answer 62

Uses current inputs as well as past OUTPUT values to produce the current output

Question 63

Non-recursive filter

Answer 63

Only uses input values to produce the current output

Question 64

Which application is the Harvard architecture very often used in and why

Answer 64

DSP applications, because harvard architectures can result in higher processing throughput which effectively determines the bandwidth of the system

Question 65

What are the advantages that the Von Neumann architecture has over Harvard architecture, and vice versa

Answer 65

``` VN advantages: - Better flexibility - Simpler hardware, especially the CU - Only need to provide 1 memory interface Harvard advantages: - 2 memory interfaces means data memory accesses and code fetches can be overlapped, therefore greater processing throughput - Doesn't suffer from VN bottleneck - Good for DSP applications ```

Question 66

Why is each register to register move (e.g. A->B) given its own opcode, instead of using a single opcode for a generic register move and specifying the source and destination registers as operands?

Answer 66

You get much quicker speed of operation with multiple opcodes, because you only have to perform one memory access. With the other method, you would need one to get the opcode and then 2 more fetches to get the operands

Question 67

Outline the process of adding 2 floating point numbers together

Answer 67

The mantissa of the number with the smaller exponent is right shifted. The number of times it is shifted is determined by the difference between the higher exponent and the lower exponent. The mantissas can then be added as normal

Question 68

Passing parameters to a procedure BY REFERENCE

Answer 68

The address of the value is pushed onto the stack

Question 69

Passing parameters to a procedure BY VALUE

Answer 69

A COPY of the parameter is pushed onto the stack

Question 70

Give an advantage and disadvantage of passing parameters to a procedure by reference

Answer 70

+ Large data structures can be passed with using just one address, so can be faster - The procedure is able to access the original data items in the calling program, so data integrity may be compromised

Question 71

Give an advantage and disadvantage of passing parameters to a procedure by value

Answer 71

+ The procedure is able to access and modify the value whilst maintaining the original value seen by the calling program - For large amounts of data, there is a time penalty and a stack space penalty

Question 72

In a serial shift and add multiplier, what is the advantage of right shifting the accumulated partial product instead of left shifting the multiplicand?

Answer 72

It means you only have to provide an n-bit wide adder and an n-bit wide multiplicand register - instead of 2n-bit wide for both

Question 73

What do you have to do to the multiplicand if you want to carry out signed shift-and-add multiplication on an unsigned multiplier?

Answer 73

You have to 'sign-extend' the multiplicand - fill it in with 1s on the left hand side. Otherwise the shift-and-add multiplier will give the wrong answer

Question 74

LIFO

Answer 74

Last in First Out. Items are pushed on and popped off. Used for stack memory to run subroutines

Question 75

Pipelining

Answer 75

Break down circuitry into stages to improve speed