Assembly Language

Question 1

What is the Von Neumann Architecture?

Answer 1

Itis archietecture model which is a concept of storing both data and instructions in the same memory space.

Question 2

What are the main components of the CPU in the von Neumann Architecture?

Answer 2

• Control Unit
• Arithmetic and Logical Unit (ALU)
• Registers (including Program Counter, Instruction Register, Address Register, Accumulator)

Question 3

What are the roles of the Program Counter, Instruction Register, and Address Register in the CPU?

Answer 3

Program counter - Address of the NEXT Instruction

Instruction register - Instruction CURRENTLY being executed or decoded

Address register - either stores the memory address from which data will be fetched, or the address to which data will sent and stored

Accumulator - SHORT - term, intermediate storage of arithmetic and logic data computations

Question 4

What is the role of the Accumulator in the CPU?

Answer 4

It serves as short-term, intermediate storage for results of arithmetic and logic computations.

Question 5

What is a system bus?

Answer 5

It is a set of physical connection which allows communication between the CPU, memory, and input/output devices.

Question 6

What are the three types of system buses in the von Neumann Architecture, and what do they carry?

Answer 6

1. Control Bus - Carries commands from the CPU and returns status signals from the devices
2. Data Bus - carries the actual data
3. Address bus - carries memory addresses from the processor to other components

Question 7

What is the role of Memory (RAM) in the von Neumann Architecture?

Answer 7

It stores both data and instructions temporarily while the system is running.

Question 8

What is the purpose of Input/Output Units in the von Neumann Architecture?

Answer 8

They allow the CPU to communicate with external devices like keyboards, screens, and storage drives.

Question 9

What does the clock cycle do in the Von Neumann Architecture?

Answer 9

It provides a high/low oscillating signal to synchronize (coordinate) CPU actions.

Question 10

How does the clock affect CPU performance?

Answer 10

• The number of clock cycles per second determines CPU speed, measured in megahertz (MHz) or gigahertz (GHz).
• The rate of the Fetch/Execute Cycle is controlled by the computer’s clock.

Question 11

How much time does a 1 GHz clock give between ticks, and what happens during that time?

Answer 11

One nanosecond per tick; the CPU tries to start the Fetch/Execute Cycle in that time.

Question 12

What is pipelining in computer architecture?

Answer 12

Pipelining is when completing an instruction is handed off to other circuitry, allowing the fetch unit to start the next instruction before the current one finishes.

Question 13

Why is it not exactly true that 1,000 instructions execute in 1,000 clock ticks?

Answer 13

Because even with pipelining, overlaps and delays mean that instructions aren’t completed perfectly one per tick.

Question 14

What are the structures in the Harvard Architecture?

Answer 14

1. Separate memory for instructions and Data
2. Parallelism

Question 15

What are the purposes of the two structures in the Harvard Architecture?

Answer 15

1. There are two memory spaces inline VNA, where one is for instructions and the other one for data
2. Instructions and data can be fetched at the same time, leading to faster execution.

Question 16

What is the MIPS R4000, and how does it differ from the von Neumann architecture?

Answer 16

The MIPS R4000 is a microprocessor without interlocked pipeline stages. It is similar to von Neumann but has separate interfaces for instructions and data, resembling a modified Harvard architecture.

Question 17

What is the significance of the “modified Harvard architecture” in the MIPS R4000?

Answer 17

It allows separate handling of instructions and data, improving performance by reducing bottlenecks in data processing.

Question 18

What are the key features of the MIPS R4000 microprocessor?

Answer 18

• First 64-bit architecture.
• Integrated caches (on-chip and off-chip secondary cache).
• Integrated Floating Point Unit (FPU).

Question 19

What was the performance and technical setup of the MIPS R4000 when it was implemented in 1992?

Answer 19

• Deep pipeline.
• 1.4 million transistors.
• Initially 100 MHz with over 50 MIPS performance.

Question 20

What makes the MIPS R4000 programming model simple and efficient?

Answer 20

It has a compact set of instructions with a regular format (MIPS III), making it easy to translate high-level code to machine language.

Question 21

Where is the IF tag check done in the MIPS R4000 pipeline?

Answer 21

The IF tag check is performed in the Register File (RF) stage.

Question 22

What happens in the IF and IS stages of the MIPS R4000 pipeline?

Answer 22

IF: First half of instruction fetch; PC selection and initiation of instruction cache access.
IS: Second half of instruction fetch; completes instruction cache access.

Question 23

What occurs during the RF and EX stages in the MIPS R4000 pipeline?

Answer 23

RF: Instruction decode, register fetch, hazard checking, and instruction cache hit detection.
EX: Execution; includes effective address calculation, ALU operations, branch target completion, and data cache access.

Question 24

Describe the functions of the DF, DS, TC, and WB stages in the MIPS R4000 pipeline.

Answer 24

DF: First half of data cache access.
DS: Second half of data fetch; completes data cache access.
TC: Tag check to determine whether the data cache access hit.
WB: Write-back for loads and register-register operations.

Question 25

What are the main components of the MIPS R4000 processor?

Answer 25

- Program counter - Instruction register - Control unit - Floating Point Unit (FPU)

Question 26

How are the registers organized in the MIPS R4000, and what are their key functions?

Answer 26

- 32 x 32-bit/64-bit registers, denoted $0-$31 (or r0-r31). - $0 (r0): Always stores 000...000. - $31 (r31): The link register used by Jump and Link instructions (should not be used by other instructions).

Question 27

How does the Arithmetic and Logic Unit (ALU) in the MIPS R4000 function?

Answer 27

- Takes input from up to two registers. - Sends output only to registers (except when calculating memory addresses).

Question 28

What is the typical process for running a program written in a high-level programming language?

Answer 28

High-level languages are compiled into assembly language, which is then assembled into binary code that the computer can execute.

Question 29

Why are high-level programming languages preferred?

Answer 29

They offer special statement forms that help programmers describe complex tasks more easily.

Question 30

What do computers actually understand, and what is the machine level?

Answer 30

Computers understand machine-level programs, which are made up of complex combinations of simple instructions

Question 31

What is an Instruction Set Architecture (ISA)?

Answer 31

An ISA is the unique set of instructions that a particular machine can understand and execute.

Question 32

What does the instruction set represent to a programmer?

Answer 32

It is the set of operations the CPU can execute — the "tools" a programmer sees and uses to control the machine.

Question 33

How do high-level and low-level programs differ in terms of instructions?

Answer 33

- High-level programs describe what and how tasks should be done. - Low-level programs also specify where operations happen (e.g., specific memory addresses or registers).

Question 34

What form must software be in for a computer to execute it?

Answer 34

Software must be in binary object code (strings of 0's and 1's).

Question 35

What is assembly language, and why is it used?

Answer 35

Assembly language is a human-readable alternative to machine language that uses letters and normal numbers to make programming easier.

Question 36

How does a computer process assembly code into binary object code?

Answer 36

1. Scans the assembly code. 2. Looks up words in a table to convert to binary. 3. Converts numbers to binary. 4. Assembles the binary pieces into complete instructions.

Question 37

What is MIPS Assembly Language, and who created it?

Answer 37

MIPS is a RISC (Reduced Instruction Set Computer) architecture created by John Hennessy and a team at Stanford University in the early 1980s.

Question 38

How does "Simplicity Favours Regularity" apply to MIPS instruction formats?

Answer 38

All MIPS instructions are the same length (32 bits) and follow a fixed format with a small number of fields, making decoding easier and hardware design simpler.

Question 39

How does MIPS maintain consistency in operand usage?

Answer 39

MIPS uses a fixed number of operands—typically two source operands and one destination operand—which speeds up hardware performance and reduces complexity.

Question 40

What does "Make the Common Case Fast" mean in MIPS architecture?

Answer 40

MIPS optimises frequently used instructions like arithmetic and load/store operations, while complex instructions are broken down into simpler ones.

Question 41

How does the Load/Store architecture contribute to MIPS efficiency?

Answer 41

In MIPS, all operations (except load and store) occur between registers, with memory access only through LW (load word) and SW (store word) instructions, simplifying execution and speeding up common operations.

Question 42

How does having a limited number of instructions make MIPS faster?

Answer 42

Using a small, simple instruction set reduces hardware complexity, allowing for faster instruction execution.

Question 43

Why does MIPS use only 32 general-purpose registers?

Answer 43

32 registers balance performance and simplicity — enough to reduce memory access without making instruction decoding and execution slower.

Question 44

How does MIPS apply the idea that "Good Design Demands Good Compromises"?

Answer 44

MIPS, as a RISC architecture, prioritizes simple and fast instructions over complex ones, balancing hardware simplicity with software flexibility.

Question 45

How does pipelining represent a design compromise in MIPS?

Answer 45

Pipelining increases instruction throughput but requires balancing longer pipelines with managing hazards from instruction dependencies.

Question 46

Why do computers use registers, and how many does MIPS have?

Answer 46

Registers provide fast storage for binary operands because main memory (RAM) is slow. MIPS has 32 fast registers.

Question 47

How are MIPS registers named, and what is special about register 0?

Answer 47

MIPS registers start with a "$", e.g., $0 is "register zero" and always holds the constant value 0.

Question 48

What are the specific uses for the $s and $t registers in MIPS?

Answer 48

- $s0-$s7 are used to store variables. - $t0-$t9 are used for holding intermediate values.

Question 49

Why do MIPS registers have limited space for data, and how is this issue handled?

Answer 49

MIPS has only 32 registers, which are small in number. To handle larger data, memory is used, but it’s slower than registers.

Question 50

What is the best practice for using registers and memory in MIPS?

Answer 50

Frequently used variables are kept in registers, while a combination of registers and memory is used to access large amounts of data quickly.

Question 51

How does the memory address calculation work with the sw (store word) instruction in MIPS?

Answer 51

The memory address is calculated by adding an offset to the base address stored in a register: address = base_register + offset.

Question 52

Can the offset in the sw instruction be written in different formats?

Answer 52

Yes, the offset can be written in either decimal (default) or hexadecimal format.

Question 53

What are three MIPS instruction types?

Answer 53

1. I-type (Immediate) 2. R-type (Register) 3. J-type (Jump)

Question 54

What does each MIPs instruction types require?

Answer 54

- Immediate require one or two registers and a value - Register require three registers - Jump require a value

Question 55

What are the three main register operands in an R-type MIPS instruction?

Answer 55

- Source1 and Source2: Source registers - Dest: Destination register

Question 56

What other fields are part of the R-type MIPS instruction format?

Answer 56

- Opcode: Operation code (0 for R-type instructions) - Shift: The shift amount (0 if not a shift instruction) - Func: The function to be performed (e.g., add, subtract, etc.)

Question 57

What are the operands in an I-type MIPS instruction?

Answer 57

- Source1 and Dest: Register operands - Value: A 16-bit immediate value

Question 58

What is the role of the Opcode in an I-type instruction?

Answer 58

- The Opcode specifies the operation to be performed. Different operations have different Opcodes.

Question 59

What is the key operand in a J-type MIPS instruction?

Answer 59

The key operand is a 16-bit value, which represents the jump target address.

Question 60

The key operand is a 16-bit value, which represents the jump target address.

Answer 60

The Opcode specifies the jump operation. Different jump operations have different Opcodes.