Based on Test 2 Q1 Flashcards
(14 cards)
State briefly what is meant by the term ‘Verification gap’
Widening gap between the exponential increase in silicon capacity (Moore’s Law, doubling every 18 months) and lagging design productivity.
How has verification gap influenced production testing for System–on–Chip (Soc) using embedded ATE functionality?
Embedding ATE functionality on–chip means the speed (bandwidth) of the silicon can be utilised and external ATE costs reduced. This is a move from ‘outside–in’ testing to ‘inside–out’ built–in self testing.
Briefly comment on how trade–offs may be made between DFT (design for test) and ATPG (automatic test pattern generation)
tl;dr: Early attention to DFT in the design cycle minimises the requirement for long test times and therefore costly ATPG. Long version: DFT required consideration early in the design flow to modify the net list to ensure thigh quality manufacturing device–under–test within available cost constraints. Direct conversion of the net list via appropriate software into test data in not possible as we have an intractable mathematical stages means more DFT effort normally means less test generation is required and vice versa. For example scan insertion DFT reduced a sequential circuit to one that is combinational enabling fast combinational ATPG e.g. D-algorithm to be used. Without scan, sequential ATPG requires significant memory resource and much longer test time.
What digital structural features impede combinational test pattern generation using D-algorithm based techniques?
Reconvergent fanout and redundancy (e.g. to eliminate race hazards in asynchronous circuitry) impede combinational ATPG.
What remedial actions in necessary on the part of the circuit designer?
Either live with certain untestable faults giving rise to reduced fault coverage or redesign the offending combinational circuitry
How can the requirement for sequential ATPF be transformed into combinational? Why is this preferred?
tl;dr: Breaking the feedback paths in a sequential circuit using scan techniques transforms the operation of the circuit–under–test (CUT) to that of a simpler combinational circuit. The number of test vectors is reduced reducing test time and test cost.
Design for test comprises ad–hoc, scan and built–in self–test techniques (BIST). State 3 attributes of ad–hoc DFT.
* Provides easier initialisation for logic simulation and design verification * Partitions the logic into easier to test pieces * Provides access to embedded blocks * Bypasses clock generation circuits (oscillators, one–shots, etc.) * Avoids or bypasses asynchronous logic * Breaks feedback loops (when they are a problem) * Breaks large counters into smaller ones * Disables intentional redundant logic for testing
How does ‘Full scan’ differ from ‘Boundary Scan’?
Full scan makes all flip–flops scannable and links them in a scan chain (shift register). Boundary scan links scan cells associated with I/O pins and several registers forming a scan chain around the periphery of a component.
What other alternative name (one word) is boundary scan’s test access port interface often referred to? How is this interface used in rapid application development?
JTAG. In–Circuit programming of Flash memory or FPGA devices
State advantages of boundary scan
* It’s a standard (IEEE 1149.1): Allows mixing components from different vendors. Provides excellent interface to internal BIST circuitry. * Well supported by CAD tool vendors, IC & ATE manufacturers * Allows testing of board & system interconnect: Back–plane interconnect test without using PCB functionality. Very high fault coverage for interconnect * Useful in diagnosis & Failure Mode Analysis: Provides component–level fault isolation. Allows real–time sampling of device on board * Useful at wafer test (fewer probes needed) BScan path reconfigured to bypass ICs not under test for faster test
Design for Test comprises ad–hoc, scan and built–in self–test techniques (BIST). State disadvantages of boundary scan.
* Overhead: Logic: About 300 gates/chip for TAP + about gates/pin. Overall overhead typicaly small (1-3%) but significant for only testing external interconnect. Especially tri–state (2 cells) & bi–directional buffers (3 cells) * I/O Pins: 4, 5 if optional TRST (test reset) pin is included * I/O delay penalty: 1 MUX delay on all input & output pins. This can be reduced by design. Internal scan design cannot have multiple chains. Cannot test at system clock speed. But internal BIST can run at system clock speed.
Design for Test comprises ad–hoc, scan and built–in self–test techniques. State attributes of BIST.
* Provides the capability of a circuit to test itself. * Can be applied hierarchically: module, chip, board or system * Provides vertical testability (same test circuitry used for all levels of testing: from chip to system
What is LBIST?
Logic BIST, Typically pseudo–random test vectors
What is MBIST? Does it typically use deterministic or pseudo–random test vectors?
Memory BIST. Typically uses deterministic test vectors as memory has a 2D regular array structure.
