chapter 19 - Paging: Faster Translations Flashcards
(10 cards)
what is a translation lookaside buffer (TLB)
cache in MMU that stores recent VPN → PFN translations
Why is the TLB important?
It avoids expensive page table lookups by quickly translating virtual addresses on a TLB hit
What happens on a TLB hit?
Use the PFN from the TLB, combine it with the offset, and directly access memory
What happens on a TLB miss?
Walk the page table in memory to find the PFN, then update the TLB with the new mapping
What is the typical structure of a TLB entry?
VPN (Virtual Page Number)
PFN (Physical Frame Number)
Valid bit
Protection bits
Who handles TLB misses?
Hardware-Managed TLB: CPU handles miss and updates TLB
Software-Managed TLB: OS handles miss via trap handler
What issue does a context switch cause for the TLB?
Old TLB entries may contain mappings for a different process → invalid!
How to solve TLB issues on context switch?
Use ASIDs (Address Space IDs) to tag TLB entries by process
Why is TLB replacement needed?
TLBs are small, and we must evict entries when it’s full
What are common TLB replacement strategies?
LRU (Least Recently Used)
Random Replacement
