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Operating Systems > Chapter 2 > Flashcards

Chapter 2 Flashcards

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1
Q

Pong game, involves user input and dot bouncing, in what three ways could we combine these two separate processes?

A
  1. Insert input processing into dot bouncing loop and stop bouncing while user enters co-ordinates. (blocking)
  2. Rewrite as Finite State Machine (non-blocking)
  3. Co-operative multitasking
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2
Q

What are the advantages and disadvantages of the blocking approach?

A

A: Simple to implement
Efficient Use of CPU

DA: One of the tasks stops while the other progresses.

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3
Q

What are the advantages and disadvantages of the FSM approach?

A

A: Efficient use of CPU

DA: Major rewrite of algorithms
Hard to understand and maintain

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4
Q

Explain co-operative multitasking.

A

Dot bouncing and user input processing are treated as semi-
independent “tasks” with their own program stacks. At strategic points in their algorithms they call swtch() function, which puts execution of the current task “on hold” and resumes execution of the other task.

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5
Q

What is execution context?

A

The minimal amount of data (contents of some registers) that must be saved to allow the program to be interrupted and later resumed.

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6
Q

What registers are not part of execution context in RISC-V?

A

t0 - t6

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7
Q

What are the advantages and disadvantages of using co-operative multitasking?

A

A: Both tasks run quasi-simultaneously
Both algorithms easy to understand.

DA: Context switching takes time, so calls to swtch() need to be placed strategically.

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8
Q

What is a processor hardware thread? Give RISC-V name.

A

A piece of hardware within CPU that can fetch and perform instructions. It has its own set of registers, program counter and control circuits.
“Hart”

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9
Q

T or F. In modern computers there is only one “Hart” per CPU as multiple would be unable to operate simultaneously.

A

False.

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10
Q

What does IRQ stand for?

A

Interrupt ReQuest

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11
Q

Explain how an IO IRQ is set up and how an interrupt goes to trap handler.

A

IRQ wire between CPU and IO adapter. When a device needs attention IRQ set to 1. CPU detects it finishs current instruction and then:

1) Sets the bit corresponding to the device in the special Cause register
2) Saves the address of the next instruction in the special Exception Program Counter (ECP) register
3) Disables all interrupts by resetting the Interrupt Enable (IE) bit in the Status register
4) Jumps to the starting address of the trap handler routine

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12
Q

Explain trap handler operation.

A

1) Saves execution context
2) Determines which peripheral device caused the interrupt and why
3) Services the device (e.g. supplies or consumes device data through MMIO registers)
4) Ensures that the device sets IRQ wire back to 0
5) Restores execution context
6) Returns to the interrupted program

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13
Q

Give three common sources of interrupts.

A

External IRQ, Timer IRQ, Software of another Hart

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14
Q

Distinguish between interrupt and software exceptions.

A

A software exception is caused by the hart itself.
An interrupt is caused by an external device.

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15
Q

List interrupt-related status and control registers of RISC-V.

List special instructions for reading and writing interrupt related control and status registers.

A

Put u or s instead of m (to get User and Supervisor Versions)
mstatus - enables overall interrupt process
mepc - content of PC at time of interrupt (address of cause)
mscratch - scratch register for machine mode
mcause - cause of the interrupt
mtvec - starting address of trap handler
mie - enables or disables interrupts
mip - holds pending interrupts

Unique to supervisor
satp - supervisor address translation and protection (virtual memory)

Reading and Writing into these
csrw (puts value from normal register into above registers)
csrr (takes value from above registers into normal register)
csrrw (puts old value of above registers into register and puts new value from register into above registers) Syntax csrrw old,above,new

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16
Q

CPU’s are fast but peripheral devices are slower. And CPU’s waiting for peripherals leads to inefficiency. What three solutions were hypothesized for this problem?

A

Batch Processing
Multi-tasking batch processing
Pre-emptive multitasking.

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17
Q

Explain Batch processing and its advantage.

A

All programs and data stored in long term memory, OS loads and
executes one after another.

No waiting for user input!

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18
Q

Explain multi-tasking batch processing and its advantage.

A

OS loads several tasks into RAM and arranges them into a queue. CPU executes a task until it starts IO on a peripheral then OS switches to next task. When peripheral loading is complete, the task is put on the queue again.

No waiting for user input and greatly reduced waiting for peripheral.

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19
Q

Why was multi-tasking batch processing not good enough?

A

Inconvenient for software development wouldn’t get results of program for a full day! Single typo would ruin a days work.

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20
Q

Explain pre-emptive multitasking and advantage.

A

Each user has own terminal
Each user starts tasks manually
Each user interacts with their tasks through the terminal.
Frequent CPU switching between tasks creates illusion that all tasks are performed in parallel.

No time is wasted for peripheral or user input (as we can do other tasks while user thinks)

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21
Q

What is a process in OS?

A

In OS, a process is an instance of running program, collection of all system resources needed to run a program. E.g. CPU time, security permissions, memory occupied and files opened.

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22
Q

Distinguish between multiprocessing and multitasking.

A

Multiprocessing: Having multiple harts, which are capable of executing multiple streams of
machine instructions simultaneously.

Multitasking: Periodically switching a single hart between multiple streams of machine instructions

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23
Q

How can execution context be used to implement multitasking, explain with example 2 Processes? Give another name for execution context?

A

Process 1 is started.
Process 1 is interrupted by Kernel
Save execution context of Process 1
Load execution context of Process 2
Process 2 is started
Process 2 is interrupted by Kernel
Save execution context of Process 2
Restore execution context of Process 1
Process 1 continues where it left off……

Process Context

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24
Q

What is process scheduling?

A

Choosing which process to resume on a particular CPU hart. Many different implementations. E.g. Round robin.

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25
How do we ensure two programs don't access MMIO registers at same time?
Programs access Kernel through ecall which then accesses MMIO registers so there is no direct access allowed as Kernel queues requests.
26
How do we ensure that only supervisor can edit registers?
Supervisor program is run in special supervisor mode.
27
What is virtual memory?
Is the way CPU sees the memory. Translate virtual memory to physical memory using a page table. Multiple processes can store things in different places but map them to the same physical (actual) address. E.g. Process 1 can say keyboard is at address 0x01 and process 2 can say keyboard is at address 0x02 but both are actually mapped to the real physical address.
28
How big is a page in size?
typically 4096 bytes.
29
Why is virtual memory good with libraries?
Avoids duplication of the same library code across multiple processes, can load library code into physical memory once and use .DLL (Win) to map code pages into virtual address spaces of all processes that use that library.
30
What is the disadvantage of virtual memory?
Threading problems, deadlock (both waiting for the other to release), race conditions (both update simultaneously so one is missed), livelock (two threads continuously releasing and reaquiring resource)
31
Explain Sv39 virtual address translation.
Memory space is divided into 4096 byte pages. LS 12 bits = memory location address Next 27 bits = virtual page number in RAM page table Sv39 page table consists of 64-bit entries indexed by the virtual page number. Each entry: 44-bit physical page number (PPN) and 10-bit flag field specifying permissions. The translated address = PPN +12-bit offset from virtual address.
32
In 10-bit flag field what does V bit mean?
If bit V = 1, page is valid so read, else generate software interrupt.
33
How is the Sv39 page table implemented.
Three-level tree of page directories (512 entries each). Each virtual page number is divided into three parts, L2, L1, and L0 - each 9 bits wide - that specify which Page Table Entry (PTE) should be selected at each level. The final level will point to the physical address.
34
Explain SATP.
Supervisor Address Translation and Protection Register (SATP) holds three sections. Mode, ASID (Address Space Idenitfier) and PPN (Physical Page Number). When Mode is set to 8, Sv39 is enabled. ASID holds virtual address space being translated. PPN of the root page table of the page table tree.
35
How do we solve the problem that individual lookups now take three four look-ups with tree page table?
Have TLB (Translation Look-aside Buffering) where recent results of virtual page translations are held, so if we look up the same number again we can get it much faster from this cache.
36
What is the locality principle?
Execution of a program usually uses a small subset of memory pages called the working set in each execution phase. If we can hold working set in TLB then lookup overhead is greatly reduced.
37
What is page thrashing?
When OS is not big enough to store active process so pages are swapped back and forth continuously from RAM. Very damaging to system performance.
38
List RISC-V privilege levels from least to most. Explain this system.
User, Supervisor, Machine. Lower <- privileged, can read higher privileged but cannot change them. System critical files cannot be changed by User.
39
Explain symmetric multiprocessor system.
All processor harts have the same level and speed of access to the Main Memory and MMIO locations. Bus Arbiter is the hardware that ensures that only one hart accesses main memory / MMIO at a time. Main memory access is a bottleneck slowing everything down. Cache is a hart-local RAM that keeps copies of frequently fetched Main Memory locations.
40
Explain Numa multiprocessor systems.
Non-Uniform Memory Access multiprocessor systems have many harts with different levels and speeds of access to different parts of a shared memory. Combines many symmetric multiprocessor systems for different purposes into a distributed shared memory network.
41
How is a critical section of code defined? (i.e. a section where we dont want to allow interrupts)
csrci mstatus,1 #disable interrupts code csrsi mstatus,1 #enable interrupts
42
What is a mutual exclusion lock?
A lock must be acquired before accessing a shared data object and released once the required operation on the object is finished. Only one thread can hold the lock at a time.
43
What does atomicity mean?
Instructions that are atomic that only one hart can perform at a time.
44
What does RiscV FENCE instruction do?
The FENCE instruction ensures that all memory accesses from instructions preceding the fence appear earlier in the global memory access order than memory accessed from instructions after the fence.
45
Show how we can use atomicity to create a lock and synchronization behavior. Add the fence instruction in the appropriate place in brackets.
Code: again: amoswap.w.aq t0, t0, (a0) bne t0,zero,again (fence iorw,iorw) Critical synchronized code ... (fence iorw,iorw) amoswap.w.rl zero, zero, (a0) First hart will set t0 to 1 and run synchronized code all other harts will see t0 = 1 and will simply keep looping until the lock is freed with last line.
46
Give an example of a monitor.
pipeline (hides synchronization implementation)
47
What do HDD and SDD stand for?
Hard Disk Drives Solid State Drives
48
Files are stored in non-volatile data storage like SSD and HDD, these contain blocks of 512 bytes, how many blocks does a mainstream file system use?
8
49
What does it mean to say SSD is non-volatile?
It means that the data stored on it is retained even when the power is turned off unlike RAM.
50
What is the role of the file subsystem in the kernel?
Read/writes block from memory. And allows process to read/write characters from file it creates.
51
What is a file (in Linux)?
A finite sequence of 8-bits akin to a piece of punched paper tape where each row represents the binary code.
52
Define root directory in Linux.
The topmost directory ("")
53
What is a link?
A connection between a directory and an ordinary file.
54
Distinguish between soft and hard link.
H: The actual file pointed to exists in multiple locations, all of these must be deleted to delete the file. Must be on same file system. Point to same i-node. S: Just a reference to the original files past. Deleting original will delete soft link. Can span different file systems. Point to reference.
55
Explain the original block device data organization in the original UNIX file system.
10 blocks 1 Superblock (contains information about types and parameters of the file system) 1 Block Allocation Bitmaps (one bit for each data block, value shows block allocation status) 2 i-node (contains all information about an individual file except name) 6 data blocks
56
What does i-node store at a minimum?
Metadata about the file except its name. File size in bytes. File type, block allocation info, link count.
57
What is the physical file called? I.e. not a reference.
Inode
58
What is an extent?
If a file is stored over multiple blocks each extent holds each group of adjoining blocks. I.e. points to first one and has number of blocks recorded.
59
What is a directory conceptually?
A list of (i-node number, file name) pairs linking file name to the specified i-node.
60
Explain how files are used for peripheral device.
When data is written to or read from a device file, it translates into MMIO access to the corresponding device by the OS kernel. Software that implements such a thing is called a device driver.
61
Explain how mounting works.
Mounting takes a directory outside of the file system and attaches it to a given name already in the file system so that the directory can be accessed within the file system.
62
How can Linux file system be dangerous?
Even information about OS processes and peripheral devices are generated continuously and stored in Linux file system. While helpful to the experienced programmer user could accidentally delete critical information.
63
How many bits are allocated to storing virtual page number is RISC-V?
27 bits

Operating Systems (4 decks)

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