Chapter 3 Flashcards
(35 cards)
What are latches?
Latches are bistable memory devices which are level
sensitive.
Draw SR Latch.
Two NOR Gates one takes S as input and output of other NOR gate.
Other takes R as input and output of original NOR GATE.
The first outputs !Q
The second outputs Q
Explain instruction set for SR latch.
SET (S = 1, R = 0) Q is high
RESET (S=0, R=1) Q is low
Memory Mode (S=0, R=0) Q does not change
Invalid (S=1, R=1)
Give truth table for ‘S’R latch using NAND gates.
‘S ‘R Q ‘Q
1 1 NC NC (No change)
0 1 1 0 (set)
1 0 0 1 (reset)
0 0 1 1 (invalid)
How does gated SR latch differ from SR latch?
If enable is on transparent, Q follows S and R, if off memory mode Q doesn’t change.
How does D latch build on gated SR latch?
Input D is S and negation of same input is R making it impossible for them to be the same.
What are flip-flops?
Flip-flops are synchronous bistable memory devices. The output of synchronous devices only changes state on the edge of a triggering control input.
What is the clock?
The clock is a signal which oscillates between 0 and 1 at a
fixed rate.
Differentiate between positive edge and negative edge.
Positive edge is when clock rises from 0 to 1.
Negative edge is when clock falls from 1 to 0.
How is a Gated SR latch adapted to an SR flip-flop?
There are two joined together.
Explain master-slave latch theory.
When clock is low, master is transparent and the slave is in memory mode.
When clock changes level the latches flip mode.
When clock goes from low to high a latch captures in the current input.
So when clock goes up master stores input, slave transparent.
When clock goes down master is transparent, slave stores master’s input.
How does a D-flip flop differ from an SR flip-flop?
Input D into S and !D into R.
How does a JK flip-flop differ from an SR flip-flop?
Input J and output !Q goes into S.
Input K AND output Q goes into R.
Explain how T flip-flop differs from JK flip-flop.
Input T is put into both J and K. So T = 0, no change and T = 1 toggle.
How is a flip flop converted into a negative edge flip-flop?
Negate clock signal.
Define a synchronous circuit.
Every circuit element is a flipflop or combinational circuit.
At least one circuit element is a flipflop
All flipflops receive the same clock signal.
Every cyclic path contains at least one flipflop.
What is a register?
A register is a group of flip-flops which store one word of data
Why is a synchronous reset required?
On power up the value stored in memory is unknown, it could be 0 or 1. So we must initialise this value.
What is an Asynchronous reset?
Built into the flip-flop to reset without need for positive edge of clock. Can lead to glitches.
Explain serial communication.
The process of sending data one bit at a time across some communication channel. Parallel-in Serial-out when transmitting. Serial-in Parallel-out when receiving.
Draw ripple adder.
Two JK flip-flops used both with asynchronous reset. High input put into J and K in both. !Q0 output of first JK flip-flop put into clock of 2nd flip-flop.
Q0 and Q1 are the important outputs. Will cycle through values 00, 01, 10, 11.
What is the state of a sequential circuit?
The value currently stored in
its memory
What is a finite state machine?
A Finite State Machine is a logic circuit which exhibits a sequence of states and is controlled by internal logic and, optionally, also by external inputs.
Distinguish between a Moore and a Mealy machine.
Moore machine, outputs only depend on the current state of the machine.
Mealy machine, outputs depend on both the current state of the machine and the current inputs.
