Chapter 3: Assembler Info

Question 1

The code to set up an area is:

Answer 1

AREA nameOfCode, CODE, READONLY
ENTRY

{code}

END

Question 2

{label} DCD v. expr {, v. expr}

Does what?

Answer 2

set up one or more 32-bit (4 byte) constant in memory. MUST START AT A MULTIPLE OF 4 ADDRESS

Question 3

{label} DCW v. expr {, v. expr}

Does what?

Answer 3

set up one or more 16-bit (2 byte) constant in memory. MUST START AT A MULTIPLE OF 2 (EVEN) ADDRESS

Question 4

{label} DCB v. expr {, v. expr}

Does what?

Answer 4

set up one or more 8-bit (1 byte) constant in memory. CAN START ANYWHERE

Question 5

{label} SPACE size (in bytes) expr

Does what?

Answer 5

reserve a zeroed block of memory

Question 6

ALIGN

Does what?

Answer 6

ensures that the next data item is correctly aligned on a 32-bit boundary (start at a multiple of 4)

Question 7

If no align is included…

Answer 7

the assembler will automatically insert bytes with zeros to ensure appropriate boundary alignment

Question 8

DCD, DCW, and DCB tell the assembler to:

Answer 8

• Reserve one or more 32-bit, 16-bit, or 8-bit blocks of storage in memory
• Load whatever values to the right of DCD, DCW, or DCB into the locations
• Advance the location-counter by one or more four, two, or one bytes so that the next instruction will be put in the next place in memory

Question 9

What is the location-counter?

Answer 9

a variable inside the assembler to keep track of memory locations during assembling a program, whereas the PC is a register to keep track of the next instruction to be executed

Question 10

What is the difference between the PC and the location-counter?

Answer 10

Location-Counter is a variable inside the assembler to keep track of memory locations during assembling a program, whereas the PC is a register to keep track of the next instruction to be executed

Question 11

ALIGN is an example of

Answer 11

explicit alignment

Question 12

Strings must

Answer 12

BE ALLOCATED WITH DCB AND DOUBLE QUOTES “ ”

Question 13

Single characters must

Answer 13

ALSO ALLOCATED WITH DCB BUT WITH SINGLE QUOTES INSTEAD ‘ ‘

Question 14

& can represent

Answer 14

DCD if used in place of DCD (P1 & 0x12345678)

0x if used after a DCD, DCW, or DCB (Strg2 = “X2”, &0C, &0A )

Question 15

= can represent

Answer 15

DCB if used in place of DCB (Strg2 = “X2”, &0C, &0A )

Question 16

% represents

Answer 16

SPACE

Question 17

A pseudo instruction is

Answer 17

an operation the programmer can use when writing code

Question 18

Pseudo instructions do not

Answer 18

Have machine language equivalents

Question 19

MOV cannot

Answer 19

move anything longer than 16-bits long (FFFF) is maximum

Question 20

Instead of using MOV for a 17+ bit literal, use

Answer 20

LDR r0, = 0xFFFFFF pseudo instruction

Question 21

LDR r0, = 0xFFFFFF pseudo instruction

Does what?

Answer 21

Loads FFFFFF into r0

Question 22

ADR r0, label

Does what?

Answer 22

loads a 32-bit address into a register

Question 23

What is the difference between ADD and ADC?

Answer 23

ADD and ADDS: adds two 32-bit values

ADC and ADCS: adds two 32-bit values together with carry

Question 24

ADDS and ADCS update which flags?

Answer 24

ADDS and ADCS update ALL FLAGS

Question 25

What is the difference between SUB and RSB?

Answer 25

SUB: SUB r1,r2,r3 means subtract r3 from r2 and store in r1 RSB: RSB r1,r2,r3 means subtract r2 from r3 and store in r1 RSB can be used to subtract from a constant: RSB r1, r2, #10 RSB can be shortened: RSB r1, #5 means RSB r1, r1, #5

Question 26

SUBS and RSBS update which flags?

Answer 26

SUBS and RSBS update ALL FLAGS

Question 27

NEG does what?

Answer 27

NEG (Negation): is a pseudo instruction to subtract a number from zero NEG only has two operands and CANNOT be shortened NEG r1, r2 is equal to RSB r1, r2, #0

Question 28

NEG r1, r2 is equal to...

Answer 28

RSB r1, r2, #0

Question 29

What is the difference between MOV and MVN?

Answer 29

MOV: MOV r0, r1 moves contents of r0 into r1 MVN: MOV r0, r1 moves the logical complement of r1 (every 1 to 0 and every 0 to 1) into r0

Question 30

MOVS and MVNS update which flags?

Answer 30

MOVS and MVNS update the N, Z, and C flags, NOT the V flag

Question 31

What does MUL do exactly?

Answer 31

MUL rd, rm, rs multiplies rm by rs and stores the lower-order 32-bits of the 64-bit operation (cannot be shortened to 2 operands) CANNOT use the same register for rd and rm ARM does not allow multiplying by a constant

Question 32

Does arm support multiplying by a constant?

Answer 32

No

Question 33

For multiplying, can you use the same register for destination and register source 1?

Answer 33

No

Question 34

For multiplying, can you use the same register for destination and register source 2?

Answer 34

Yes

Question 35

MLA does what?

Answer 35

MLA: MLA rd, rm, rs, rn = (rm x rs) + rn. Cannot be shortened to three operands

Question 36

MULS and MLAS update which flags?

Answer 36

MULS and MLAS update the N and Z flags, but CORRUPT the C and V flags

Question 37

MVN does what to 11001010?

Answer 37

will not EVERY bit, INCLUDING the leading zeros: 11111111111111111111111100110101

Question 38

ANDS, ORRS, EORS, and MVNS update which flags?

Answer 38

ANDS, ORRS, EORS, and MVNS update the N, Z, and C flags, NOT the V flag

Question 39

What does the 2_ sign prefix indicate?

Answer 39

Binary

Question 40

What does the 8_ sign prefix indicate?

Answer 40

Octal

Question 41

What does the 0x sign prefix indicate?

Answer 41

Hexadecimal

Question 42

What does the & sign prefix indicate?

Answer 42

Hexadecimal

Question 43

BIC does what?

Answer 43

BIC (bit clear) ANDs its first operand with the complement of the second Example: suppose we have r1 = 10101010 and r2 = 00001111. The instruction BIC r0, r1, r2 yield 10100000

Question 44

BICS updates which flags?

Answer 44

BICS updates the N, Z, and C flags, NOT the V flag

Question 45

What is the difference between implicit and explicit updating of flags?

Answer 45

Example of implicit updates for the condition flags: SUBS r1,r1,r2 Example of explicit updates for the condition flags CMP r1,r2

Question 46

What does CMP r1, r2 do?

Answer 46

evaluates r1 - r2 and sets the flags without storing the result

Question 47

What does TEQ r1, r2 do?

Answer 47

Tests whether r1 is equal to r2 | similar to EORS, except that the result is discarded

Question 48

What does TST r1, r2 do?

Answer 48

TST (test instruction) Compares two operands by ANDing them together and update flags. Usually used to test individual bits; TST r0, #2_00100000 ;AND r0 with 00100000 to test bit 5

Question 49

What does CMN r1, r2 do?

Answer 49

CMN (compare negative instruction). 2’s complements the second operand before performing the comparison: CMN r1, r2 ; evaluates [r1] – (-[r2])

Question 50

What is a logical shift?

Answer 50

Insert a 0 in the vacated positions

Question 51

What is an arithmetic shift?

Answer 51

replace the sign bit during a right shift

Question 52

What is a circular shift?

Answer 52

the bit shifted out of one end is places into the other

Question 53

What is a Circular shifts through carry?

Answer 53

Include the carry bit in the shift path

Question 54

Does arm have any explicit shift operation?

Answer 54

No

Question 55

What can ARM do with shift operations?

Answer 55

ARM can combine shifting operations with other data processing operations where the second operand is allowed to be shifted BEFORE it is used ADD r0,r1,r2,LSL #1 ; [r0] < [r1] + [r2] × 2

Question 56

LSL r3, r3, #1 is equal to

Answer 56

MOV r3, r3, LSL #1 which is equal to LSL r3, #1

Question 57

MOV r3, r3, LSL #1 is equal to

Answer 57

LSL r3, r3, #1 which is equal to LSL r3, #1

Question 58

LSL is a

Answer 58

pseudo instruction

Question 59

ARM supports both ____ and ____ shifts

Answer 59

Static and dynamic

Question 60

For LSL, allowable values are from

Answer 60

#0 to #31 (32 different values)

Question 61

For LSR, allowable values are from

Answer 61

#1 to #32 (32 different values)

Question 62

For ASR, allowable values are from

Answer 62

#1 to #32 (32 different values)

Question 63

For ROR, allowable values are from

Answer 63

#1 to #31 (31 different values)

Question 64

For dynamic shifts, the following mean what? MOV r4,r3,LSL r2 LSL r4,r3,r2

Answer 64

MOV r4,r3,LSL r2 ; [r4] [r3] × 2^r2 LSL r4,r3,r2 ;[r4] [r3] × 2^r2

Question 65

If, for a shift operation, the value of the register storing the dynamic amount is greater than 32, what will be stored in the destination?

Answer 65

Zeros

Question 66

What are the five shift types supported by ARM?

Answer 66

LSL logical shift left LSR logical shift right ASR arithmetic shift right ROR rotate right RRX rotate right through carry (one shift)

Question 67

Arithmetic shift left is the same as

Answer 67

a logical shift left

Question 68

Rotate left through carry can be implement by

Answer 68

ADCS r0,r0,r0 ; add r0 to r0 with carry and set the flags The instruction means r0 + r0 + C, i.e., 2 × r0 + C

Question 69

What are the two ways of loading addresses into a register?

Answer 69

LDR r0, =PPP | ADR r0, PPP

Question 70

What is the order of the data definition if it were to be negative, and hex? Octal?

Answer 70

``` #-0xFC = hex Starts with the # sign Followed by the optional positive or negative sign Followed by an optional base sign Followed by the number ``` #-8_15 = octal