Chapter 3: ISA & Intro to Assembly

Question 1

For a stored program computer, the CPU…

Answer 1

reads instructions from memory and executes them

Question 2

For a stored program computer, temporary data is stored…

Answer 2

in registers

Question 3

For a stored program computer, the PC

Answer 3

(Program Counter) is a register that points at the next instruction (inside the memory) to be executed

Question 4

For a stored program computer, the CCR

Answer 4

(Condition Code Register) contains the flag bits for the processor

Question 5

Computers can execute instructions ranging from

Answer 5

8-bits wide to multi-bytes wide

Question 6

The instruction format defines the anatomy of an instruction:

Answer 6

• Number of operands
• Number of bits devoted to defining each operation
• Format of each operation

Question 7

The PC is

Answer 7

(Program Counter) points to the next instruction and is incremented after each execution

Question 8

The stored-program computer operates in a

Answer 8

fetch/execute two-phase mode

Question 9

In the stored-program computer’s fetch mode:

Answer 9

the next instruction is read from memory AND decoded

Question 10

In the stored-program computer’s execute mode:

Answer 10

the instruction is interpreted and executed according to the CPU’s logic

Question 11

What is pipelining?

Answer 11

When fetch and execute operations overlap

Question 12

What are the features of a stored program computer?

Answer 12

• Register file (r0-ri)
• PC (Program Counter)
• IR (Instruction Register)
• MAR ( Memory Address Register)
• MBR (Memory Buffer Register)

Question 13

What is the Register File?

Answer 13

(r0-ri) is a set of general-purpose registers that store temporary working data

Question 14

A computer requires at least one ______ register

Answer 14

General purpose

Question 15

What is the PC

Answer 15

(Program Counter) contains the address of the next instruction to be executed. I.e points to the location in memory containing the next instruction

Question 16

What is the IR

Answer 16

(Instruction Register) holds the instruction most recently read from memory (the instruction currently being executed)

Question 17

What is the MAR

Answer 17

(Memory Address Register) stores the address of the location in main memory that is currently being accessed by either a read or write operation

Question 18

What is the MBR

Answer 18

(Memory Buffer Register) stores the data that has just been read from main memory OR data that is to be written to main memory

Question 19

In the fetch-phase, the PC…

Answer 19

(Program Counter) supplies the address of the next instruction to be executed to the MAR (Memory Address Register) and is incremented by the size of an instruction

Question 20

In the fetch-phase, the MAR…

Answer 20

(Memory Address Register) reads the instruction which will be sent to the MBR

Question 21

In the fetch-phase, the MBR…

Answer 21

Receives the instruction pointed at by the MAR and sends it to the IR

Question 22

In the fetch-phase, the IR…

Answer 22

Receives the instruction from the MBR and decodes it

Question 23

In the execute-phase, operands may be…

Answer 23

read from the register file or transferred to the ALU (Arithmetic Logic Unit) where they are operated on

Question 24

In the execute-phase, if the operation requires memory access, the address is read from the …

Answer 24

IR

Question 25

In the execute-phase, if the operation requires memory access, the address is sent to the...

Answer 25

MAR

Question 26

In the execute-phase, if the operation requires memory access, the contents of the memory address are placed in the...

Answer 26

MBR

Question 27

In the execute-phase, if the operation requires memory access, the contents of the MBR are finally placed in the...

Answer 27

Register

Question 28

With constants, the IR (Instruction Register) paths the literal operand to either the...

Answer 28

Register file, the ALU, or the MBR

Question 29

Flow control is

Answer 29

action that modifies the normal instruction sequence

Question 30

Conditional behavior allows

Answer 30

the processor (based on the CCR flags) to select one of two courses of action: - Continue executing the next instruction in sequence - Load the PC with a new value and executing a branch of another region of code

Question 31

The root of flow control is

Answer 31

The ALU which determines the flags of the CCR

Question 32

The CCR is determined by the

Answer 32

ALU

Question 33

The four status flags are:

Answer 33

Zero (Z) flag if the result is zero Negative (N) flag (in two’s complement) if the result is negative Carry (C) flag if the result generated a carry-out oVerflow (V) flag if the result generated arithmetic overflow

Question 34

In terms of status flags, the difference between CISC and RISC is

Answer 34

CISC (Complex Instruction Set Computer) automatically sets the status flags after each operation RISC (Reduced Instruction Set Computer) requires the programmer to request to update the flags

Question 35

In ARM, general purpose registers can be used for

Answer 35

Anything

Question 36

In ARM, there are __ specific purpose registers

Answer 36

2

Question 37

Registers in arm are how many bits wide?

Answer 37

32 (4 bytes)

Question 38

What are the two addressing modes supported by ARM?

Answer 38

Literal/immediate and register-indirect/pointer-based/indexed

Question 39

What addressing mode is not supported by ARM?

Answer 39

Direct/absolute

Question 40

What is Literal/immediate addressing?

Answer 40

the actual value is part of the instruction

Question 41

What is direct/absolute addressing?

Answer 41

the instruction contains the memory address of the instruction

Question 42

What is register-indirect/pointer-based/indexed addressing?

Answer 42

the register contains the address of the operand

Question 43

What are the three types of instructions?

Answer 43

Memory-to-register Register-to-memory Register-to-register

Question 44

What instruction type is supported by ARM?

Answer 44

Register-to-register

Question 45

LDR and STR are special forms of what?

Answer 45

pseudo-instructions

Question 46

In terms of the amount of addresses that can be stored in an instruction, CISC has ___ and RISC has ___ typically

Answer 46

CISC: 2 RISC: 3

Question 47

RISC typically has ___ address instructions where they are all ___

Answer 47

3 address instructions which are all registers

Question 48

Does RISC support 3 memory address instructions?

Answer 48

NO

Question 49

Does RISC support 3 register instructions?

Answer 49

Yes

Question 50

What does ARM stand for?

Answer 50

Advanced RISC Machines

Question 51

In ARM, a half-word is ____ bits and a full word is ____ bits

Answer 51

A half word is 2 bytes (16 bits) A full word is 4 bytes (32 bits)

Question 52

ARM's register set has ___ registers

Answer 52

16 registers

Question 53

ARM's general purpose registers are:

Answer 53

r0 - r12

Question 54

ARM's PC register is r__

Answer 54

r15

Question 55

ARM's CPSR stands for

Answer 55

Current Program Status Register

Question 56

ARM's CPSR contains flag bits at what indexes?

Answer 56

28, 29, 30, 31

Question 57

What are the two types of ARM statements?

Answer 57

Executable instructions Assembler directives

Question 58

Assembler directives are:

Answer 58

Statements that tell the assembler something about the environment

Question 59

Executable Instructions are...

Answer 59

Statements that are executed by the computer

Question 60

Lines to be executed by the computer are called

Answer 60

Executable Instructions

Question 61

Lines that tell the assembler something about the environment are called

Answer 61

Assembler Directives