Chapter 4 Processor fundamentals Flashcards
(32 cards)
Stored program concept
instructions and data are stored in same memory space// main memory
Components of Von Neumann Architecture
-Buses, Registers, CPU , CU, ALU, IAS, System Clock
General Purpose registers
-hold temporary data when performing operations
-used for any purpose
-can be used by most intrustions
Special Purpose registers
-Hold status of a prgram
-Specialised for Specific use
-can only be used by certain instructions
Program Counter
-Holds address of the next instruction to be loaded
-Is incremented once an instruction has been carried out
Memory Address Register
-stores memory address of memory location currently being read from or written too (where dtaa is being fetched from)
Memory Data Register
-Holds data feteched from address in MAR
-Data is copied into CIR
Current Instruction Register
-Holds data from MDR
-holds instruction currently being decoded/executed
Index Register
-stores value that is added to an address to make another address
CU
-synchronissies actions of other components in CPU
-Sends/receives control signals along control bus
-manages the execution of instructions/ decodes an instructions opcode during FE cycle
-controls communications between components in CPU
-types of signals it transfers- interrupts, timing, read and write
Status Register
-stores flags from results of logic arithmetic operations//interrupt flags
-contains bits, can be indvidually set or cleared depending on operation
Immidiate Access Store
-Holds data/programs currently in use
-Voltile memory
-has fast access times
System Clock
-synchronises computer operations using timing signals
-allows operations to proceed in correct order/sequence
-keeps track of date and time
How data is transferred between componenets
-system clock gives out signals sent on the control bus this synchronises the other system components
-CU initialises data transfer, generates signals sent on the control bus to other components
Roles of buses
Data bus-carries data between devices, buffer or components
Address Bus-carries address where data is going or will be written to or read from
Number of cores
-each core processes one clock instruction per clock pulse
-more cores means more sequences of instructions of instructions can be carried out simultaneously
-multiple instructions can be executed per clock pulse
-decreased time taken to complete task
Issues
-software may not be designed for multiple cores, one core will be left idle
-memory access speed wont match speed of cores causing delays
-may be other differences, amount of RAM
Bus Width
allow transfer of more data each time
Clock Speed
-Each instruction is carried out on clock pulse
-clock speed dictates the rate at which instructions are being run
-Faster clock speed = more instructions can be run per unit second
Cache
-higher capacity means it can store higher amount of frequently used instructions for faster access
-fast memory access as close to CPU
-stores frequently used intruction/data
-more cache means more instructions can be transferred faster, less swapping between RAM and cache
-prevents CPU idling while waiting for data
Quality of RAM
-more applications can reside in main memory simultaneously
-saves/decreases disk access time
Ports
-purpose to provide connections to peripherals and provide interface between computer and other devices
USB//COM port
-faster data transfer speed
-universal standard
-1 bit transferred at at a time
-can be asynchrounous and synchronous
-USB-3 full duplex other wise half duplex
HDMI
-digital interface
-transmits high quality audio and video
-supports copy protection
VGA
-analog interface
-transmits video only
-prone to signal degration over long cables
Display Port
-digital inteface
-supports higher resolutions
-both video and audio
Fetch Execute Cycle
-PC stores address of next instruction to be fetched + contents are incremented each cycle
-MAR hold address of where data is fetched from (from where data will be read to or written from)
-MDR holds data from address at MAR
-instruction from MDR copied to CIR for decoding and execution
Notation
-[PC] <– [PC] + 1
-MAR<–[PC]
-MDR<– [[MAR]]
-CIR <–[MDR]
Stages of FE cycle
-next address to be fetched is stored in PC
-this address copied to MAR using address bus
-instruction in that address is copied from main memory to MDR using data bus
-instruction copied from MDR to CIR
-Instruction decoded by CIR (intoopcode and operand)
-processor executes instruction
-address in PC is incremented
Interups
Purpose
-to send signal from device/process
-seeking attention of processor
Causes of Software Interupts
-division by zero//runtime error
-attempt to access invalid memory location
-array index out of bounds
-stack overflow
-buffer overflow
Causes of Hardwere interupts
-printer out of paper
-keyboard key press
-power failiure
