Chapter 5 - The Processor

Question 1

an operation element, such as an AND gate or an ALU

Answer 1

Combinational element

Question 2

a memory element, such as a register or a memory

Answer 2

State element

Question 3

the approach used to determine when data is valid and stable relative to the clock

Answer 3

Clocking methodology

Question 4

a clocking scheme in which all state changes occur on a clock edge

Answer 4

Edge-triggered clocking

Question 5

a signal used for multiplexor selection or for directing the operation of a functional unit, contrast with a data signal, which contains information that is operated on by a functional unit

Answer 5

Control signal

Question 6

the signal is logically high or true

Answer 6

Asserted

Question 7

the signal is logically low or false

Answer 7

Deasserted

Question 8

a unit used to operate on or hold data within a processor. In the LEGv8 implementation; includes the instruction and data memories, the register file, the ALU and adders.

Answer 8

Datapath element

Question 9

the register containing the address of the instruction in the program being executed

Answer 9

Program counter

Question 10

a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.

Answer 10

Register file

Question 11

the address specified in a branch, which becomes the new program counter if the branch is taken In the LEGv8 architecture, the branch target is given by the sum of the offset field of the instruction and the address of the branch

Answer 11

Branch target address

Question 12

a branch where the branch condition is satisfied and the program counter becomes the branch target. All unconditional branches are taken branches

Answer 12

Branch taken

Question 13

a branch where the branch condition is false and the program counter becomes the address of the instruction that sequentially follows the branch

Answer 13

Branch not taken or (untaken branch)

Question 14

form logic, a representation of a logical operation by listing all the values of the inputs and then in each case showing what the resulting outputs should be

Answer 14

Truth table

Question 15

an element of a logical function in which the output does not depend on the values of all the inputs. may be specified in different ways

Answer 15

Don’t-care term

Question 16

also called single clock cycle implementation. An implementation in which an instruction is executed in one clock cycle. While easy to understand. It is too slow to be practical

Answer 16

Single-cycle implementation

Question 17

an implementation technique in which multiple instructions are overlapped in execution, much like an assembly line

Answer 17

Pipelining

Question 18

when a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination or instructions that are set to execute

Answer 18

Structural hazard

Question 19

When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available

Answer 19

Data hazard (pipeline data hazard)

Question 20

also called bypassing. A method of resolving a data hazard by retrieving the missing the data element from internal buffers rather than waiting for it to arrive from programmer visible registers or memory

Answer 20

Forwarding

Question 21

a specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction

Answer 21

Load-use data hazard

Question 22

also called bubble. A stall initiated in order to resolve a hazard

Answer 22

Pipeline stall

Question 23

also called branch hazard. When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected

Answer 23

Control hazard

Question 24

a method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome

Answer 24

Branch prediction

Question 25

the number of stages in a pipeline or the number of stages between two instructions during execution

Answer 25

Latency

Question 26

to discard instructions in a pipeline, usually due to an unexpected event

Answer 26

Flush

Question 27

also called interrupt. An unscheduled event that disrupts program execution, used to detect overflow

Answer 27

Exception

Question 28

an interrupt for which the address to which control is transferred is determined by the cause of the exception

Answer 28

Vectored interrupt

Question 29

interrupts or exceptions in pipelined computer that are not associated with the exact instruction that was the pause of the interrupt or exception

Answer 29

Imprecise interrupt

Question 30

An interrupt or exception that is always associated with the correct instruction in pipelined computers

Answer 30

Precise interrupt (precise exception)

Question 31

the parallelism among instructions

Answer 31

Instructions-level parallelism

Question 32

a scheme whereby multiple instructions are launched in one clock cycle

Answer 32

Multiple issue

Question 33

an approach to implementing a multiple-issue processor where many decisions are made by the compiler before execution

Answer 33

Dynamic multiple issue

Question 34

the position from which instructions could issue in a given clock cycle

Answer 34

Issue slot

Question 35

an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions

Answer 35

Speculation

Question 36

the set of instructions that issues together in one clock cycle; may be determined statically by the compiler or dynamically by the processor

Answer 36

Issue packet

Question 37

a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields

Answer 37

Very long instruction word

Question 38

number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline

Answer 38

Use latency

Question 39

a technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together

Answer 39

Loop unrolling

Question 40

the renaming of registers by the compiler or hardware to remove antidependences

Answer 40

Register renaming

Question 41

also called name dependence. An ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions

Answer 41

Antidependences

Question 42

an advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution

Answer 42

Superscalar

Question 43

hardware support for reordering the order of instruction execution to avoid stalls

Answer 43

Dynamic pipeline scheduling

Question 44

the unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory

Answer 44

Commit unit

Question 45

a buffer within a functional unit that holds the operands and the operation

Answer 45

Reservation station

Question 46

the buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register

Answer 46

Reorder buffer

Question 47

a situation in pipelined execution when an instruction blocked from execution does not cause the following instructions to wait

Answer 47

Out-of-order execution

Question 48

a commit in which the results or pipelined execution are written to the programmer visible state in the same order that instructions are fetched

Answer 48

In order commit