Comp Organization GeeksForGeeks 11 - 20

Question 1

Reduced Instruction Set Architecture (RISC)

Answer 1

The main idea behind this is to make hardware simpler by using an instruction set composed of a few basic steps for loading, evaluating, and storing operations just like a load command will load data, a store command will store the data.

Reduce the cycles per instruction at the cost of the number of instructions per program.

Question 2

Complex Instruction Set Architecture (CISC)

Answer 2

The main idea is that a single instruction will do all loading, evaluating, and storing operations just like a multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s complex.

The CISC approach attempts to minimize the number of instructions per program but at the cost of an increase in the number of cycles per instruction.

Question 3

Characteristics of RISC

Answer 3

Simpler instruction, hence simple instruction decoding.

Instruction comes undersize of one word.

Instruction takes a single clock cycle to get executed.

More general-purpose registers.

Simple Addressing Modes.

Fewer Data types.

A pipeline can be achieved.

Question 4

Characteristics of CISC

Answer 4

Complex instruction, hence complex instruction decoding.

Instructions are larger than one-word size.

Instruction may take more than a single clock cycle to get executed.

Less number of general-purpose registers as operations get performed in memory itself.

Complex Addressing Modes.

More Data types.

Question 5

Example – Suppose we have to add two 8-bit numbers:

Answer 5

CISC approach: There will be a single command or instruction for this like ADD which will perform the task.

RISC approach: Here programmer will write the first load command to load data in registers then it will use a suitable operator and then it will store the result in the desired location.

Question 6

Advantages of RISC

Answer 6

Simpler instructions: RISC processors use a smaller set of simple instructions, which makes them easier to decode and execute quickly. This results in faster processing times.

Faster execution: Because RISC processors have a simpler instruction set, they can execute instructions faster than CISC processors.

Lower power consumption: RISC processors consume less power than CISC processors, making them ideal for portable devices.

Question 7

Disadvantages of RISC

Answer 7

More instructions required: RISC processors require more instructions to perform complex tasks than CISC processors.

Increased memory usage: RISC processors require more memory to store the additional instructions needed to perform complex tasks.

Higher cost: Developing and manufacturing RISC processors can be more expensive than CISC processors.

Question 8

Advantages of CISC

Answer 8

Reduced code size: CISC processors use complex instructions that can perform multiple operations, reducing the amount of code needed to perform a task.

More memory efficient: Because CISC instructions are more complex, they require fewer instructions to perform complex tasks, which can result in more memory-efficient code.

Widely used: CISC processors have been in use for a longer time than RISC processors, so they have a larger user base and more available software.

Question 9

Disadvantages of CISC

Answer 9

Slower execution: CISC processors take longer to execute instructions because they have more complex instructions and need more time to decode them.

More complex design: CISC processors have more complex instruction sets, which makes them more difficult to design and manufacture.

Higher power consumption: CISC processors consume more power than RISC processors because of their more complex instruction sets.

Question 10

microprocessor

Answer 10

processing unit on a single chip. It is an integrated circuit that performs the core functions of a computer CPU. It is a multipurpose programmable silicon chip constructed using Metal Oxide Semiconductor (MOS) technology which is clock-driven and register-based. It accepts binary data as input and provides output after processing it as per the specification of instructions stored in the memory. These microprocessors are capable of processing 128 bits at a time at the speed of one billion instructions per second.

Question 11

Characteristics of microprocessor

Answer 11

Instruction Set –
The set of complete instructions that the microprocessor executes is termed the instruction set.

Word Length –
The number of bits processed in a single instruction is called word length or word size. Greater the word size, the larger the processing power of the CPU.

System Clock Speed –
Clock speed determines how fast a single instruction can be executed in a processor. The microprocessor’s pace is controlled by the System Clock. Clock speeds are generally measured in millions of cycles per second (MHz) and thousand million cycles per second (GHz). Clock speed is considered to be a very important aspect of predicting the performance of a processor.

Question 12

memory to memory architecture

Answer 12

In memory to memory architecture, source operands, intermediate and final results are retrieved (read) directly from the main memory. For memory to memory vector instructions, the information of the base address, the offset, the increment, and the vector length must be specified in order to enable streams of data transfers between the main memory and pipelines. The processors like TI-ASC, CDC STAR-100, and Cyber-205 have vector instructions in memory to memory formats. The main points about memory to memory architecture are:
There is no limitation of size
Speed is comparatively slow in this architecture

Question 13

microprocessor classification:
EPIC

Answer 13

It stands for Explicitly Parallel Instruction Computing. The best features of RISC and CISC processors are combined in the architecture. It implements parallel processing of instructions rather than using fixed-length instructions. The working of EPIC processors is supported by using a set of complex instructions that contain both basic instructions as well as the information of execution of parallel instructions. It substantially increases the efficiency of these processors.

Question 14

microprocessor classification:
CISC

Answer 14

It stands for Complex Instruction Set Computer. These processors offer the users, hundreds of instructions of variable sizes. CISC architecture includes a complete set of special-purpose circuits that carry out these instructions at a very high speed. These instructions interact with memory by using complex addressing modes. CISC processors reduce the program size and hence lesser number of memory cycles are required to execute the programs. This increases the overall speed of execution.
Examples: Intel architecture, AMD

Question 15

Register to register architecture

Answer 15

In register to register architecture, operands and results are retrieved indirectly from the main memory through the use of large number of vector registers or scalar registers. The processors like Cray-1 and the Fujitsu VP-200 use vector instructions in register to register formats. The main points about register to register architecture are:
Register to register architecture has limited size.

Speed is very high as compared to the memory to memory architecture.

The hardware cost is high in this architecture.

Question 16

Accumulator (ACC)

Answer 16

Holds the intermediate results of computations.
Used for arithmetic and logical operations.

Question 17

Status register

Answer 17

Holds status information about the processor and the current instruction.
Used to indicate whether an operation was successful, to set and clear flags, and to store error information.

Question 18

Index register (IX)

Answer 18

Holds an offset value to be added to a memory address.
Used to access data structures or arrays.

Question 19

Stack pointer (SP)

Answer 19

Holds the memory address of the last item placed on the stack.
Used for managing the program stack during function calls and returns.

Question 20

registers work together to perform instruction execution. The program counter fetches the next instruction, which is stored in the instruction register. The instruction is decoded and the memory address to be accessed is stored in the memory address register. The data is then accessed from memory and stored in the memory data register.

Answer 20

The accumulator holds the intermediate results of computations, and the status register holds the status information. The index registers and stack pointer are used for accessing data structures and managing the program stack during function calls and returns. Together, these essential registers enable the processor to execute instructions efficiently and accurately.

Question 21

The main points about Single Accumulator based CPU Organisation are:

In this CPU Organization, the first ALU operand is always stored into the Accumulator and the second operand is present either in Registers or in the Memory.

Accumulator is the default address thus after data manipulation the results are stored into the accumulator.

One address instruction is used in this type of organization.

Answer 21

he format of instruction is: Opcode + Address
Opcode indicates the type of operation to be performed.
Mainly two types of operation are performed in a single accumulator based CPU organization:

1. Data transfer operation –
   In this type of operation, the data is transferred from a source to a destination.

For ex: LOAD X, STORE Y
Here LOAD is a memory read operation that is data is transferred from memory to accumulator and STORE is a memory write operation that is data is transferred from the accumulator to memory.

2. ALU operation –
   In this type of operation, arithmetic operations are performed on the data.

For ex: MULT X
where X is the address of the operand. The MULT instruction in this example performs the operation,

AC <– AC * M[X]
AC is the Accumulator and M[X] is the memory word located at location X.

This type of CPU organization is first used in PDP-8 processors and is used for process control and laboratory applications. It has been totally replaced by the introduction of the new general register-based CPU.

Question 22

Advantage of Single accumulator

Answer 22

One of the operands is always held by the accumulator register. This results in short instructions and less memory space.

The instruction cycle takes less time because it saves time in instruction fetching from memory.

Question 23

DIsadvantages of single accumulator

Answer 23

When complex expressions are computed, program size increases due to the usage of many short instructions to execute it. Thus memory size increases.

As the number of instructions increases for a program, the execution time increases.