Computer Architecture

Question 1

Fill in the blank: A memory unit in Von Neumann Architecture stores _______.

Answer 1

data and instructions

Question 2

What is pipelining in processor architecture?

Answer 2

Overlapping operations to improve efficiency

Question 3

What problem occurs in in-order pipelines?

Answer 3

Pipeline stall / Execution Bubble

Question 4

What are the types of instruction dependences?

Answer 4

• Read after Write (RAW)
• Write after Read (WAR)
• Write after Write (WAW)

Question 5

What is out-of-order execution?

Answer 5

Allows instructions to be executed in a different order than they appear in the program to maximize resource utilization

Question 6

What is the role of the Branch Prediction Unit (BPU)?

Answer 6

Tracks branch addresses and their statuses in a BTB (Branch Target Buffer) structure

Question 7

What is the difference between a single and double bit branch predictor?

Answer 7

Double bit branch predictor takes last 2 predictions into account (vs. last) and changes prediction in case of 2 mispredictions (vs. 1).

Question 8

Name 3 static branch predictions

Answer 8

if => not taken
for => taken
call / return => taken

Question 9

What does SIMD stand for?

Answer 9

Single Instruction, Multiple Data

Question 10

What is the purpose of SIMD execution?

Answer 10

To execute the same operation on multiple data elements

Question 11

List the types of data supported by SIMD instruction sets.

Answer 11

• 8x long
• 16x int
• 32x short
• 64x char

Question 12

What is a fused instruction in SIMD?

Answer 12

Combines two operations, such as multiply and add

Question 13

What is the main advantage of superscalar execution?

Answer 13

Parallely executing different instructions or the same instruction on different data

Question 14

What does Simultaneous Multi-Threading (SMT) aim to achieve?

Answer 14

Feed multiple instruction streams into execution units

Question 15

What is the function of a Reorder Buffer in out-of-order execution?

Answer 15

Restores original instruction order before committing results

Question 16

What is the effect of a pipeline bubble?

Answer 16

Pipeline stalls until the long operation is finished

Question 17

What is an example of a dynamic branch predictor?

Answer 17

2-bit predictor (saturating counter)

Question 18

Fill in the blank: In SIMD, load and store operations transfer data from _______ to registers.

Answer 18

memory/caches

Question 19

What does the term ‘out-of-order pipelining’ refer to?

Answer 19

Exploiting instruction independence in a linear stream

Question 20

How does branch prediction impact performance in pipelines?

Answer 20

Reduces stalls caused by conditional branches

Question 21

What is the purpose of the instruction ‘vaddpd’?

Answer 21

To perform a vector addition of packed double-precision floating-point elements

‘vaddpd’ stands for Vector Add Packed Double-Precision Floating-Point.

Question 22

What does ‘Fused Instructions’ refer to?

Answer 22

Two operations fused into one SIMD instruction

Example: multiply and add operations.

Question 23

What is the significance of the number ‘256’ in the context of SIMD instructions?

Answer 23

It indicates the width of the SIMD instructions in bits

This often relates to the data that can be processed simultaneously.

Question 24

What is the function of the ‘vfmadd213ps’ instruction?

Answer 24

It computes fused multiply-add of packed single-precision floating-point elements

This instruction performs multiplication followed by addition in one step.

Question 25

What does 'Conditional Evaluation' mean in SIMD instructions?

Answer 25

It limits the effect of instructions to a subset of SIMD elements using a mask register ## Footnote This allows selective processing of data.

Question 26

Fill in the blank: The instruction 'vbroadcast' is used to _______.

Answer 26

[assign a scalar value to all SIMD elements]

Question 27

What is the purpose of shuffle and swizzle instructions in SIMD?

Answer 27

To modify data layout in the SIMD register ## Footnote Examples include separating real and imaginary parts of complex numbers.

Question 28

What does 'vpermilpd' do?

Answer 28

It permutes packed double-precision floating-point elements within a single operand ## Footnote This instruction allows for specific reordering of data elements.

Question 29

What is the role of 'vperm2f128'?

Answer 29

To permute 128-bit chunks from two source operands into a destination ## Footnote This is useful for rearranging data in SIMD processing.

Question 30

What is the meaning of 'Non-uniform memory access' in the context of processor architecture?

Answer 30

It refers to memory access times that vary based on the memory location relative to the processor ## Footnote This affects performance and efficiency in memory-intensive applications.

Question 31

How does branch prediction help?

Answer 31

helps avoid pipeline stalls by speculating the correct execution path and determining in advance which instruction should be fetched next

Question 32

What are the 2 locality principles of caches?

Answer 32

Temporal Locality: data items accessed will be accessed again in the future Spacial Locality: data items accessed are close to each other

Question 33

What is the difference between inclusive and non-inclusive cache?

Answer 33

Inclusive caches keep copy of a cache line in each level Non-inclusive caches evict higher cache levels copy

Question 34

Name 2 cache issues

Answer 34

Compulsory Cache Miss (initial access to data will always be a miss) Capacity Cache Miss (data evicted before it can be reused because too large for the cache)

Question 35

Which effect do memory fences have?

Answer 35

re-ordering of mem operations in the out-of-order engine is restricted

Question 36

What should be considered when using a shared variable among threads given a relaxed consistency model?

Answer 36

OOO execution might rearrange load and store operations depending on the memory consistency model

Question 37

What is snoop filtering?

Answer 37

Snoop filtering reduces unnecessary coherence traffic by tracking which cache lines are present in each core’s cache, preventing redundant snoop requests when a cache miss occurs