Computer Systems Flashcards

Question

Register

Answer 1

Number of flip flops bundled together that can be accessed in parallel. can contain input output for an adder can store memory address of current instructions.

Answer 2

shifts content left or right. Each step one bit is lost and 0 bit is inserted. n/2 if right n x2 if left shift

Answer 3

gate delays to react on a changed input use a clock as it sets pc to sleep and wake them up again.

Answer 4

xi = c : assignment c is any natural number xi = x +1 xi = x-1 if xi != 0 then goto Mn ( marker n) example 02

Answer 5

00 x1 = c 01 x2 = d 02 x2 = x2+1 x1 = x1 -1 if x1 != 0 then goto 02

Answer 6

xn = xn + xm xn = xn - xm xn = xn x xm if xn != 0 then goto line

Answer 7

contains memory address for value for Data register 1 contains memory address for value for Data register 2 Register containing address of current instruction Contains current instruction increases content of IP by 1 Contains first operand for additrion

Answer 8

JUMP - if DR1 != 0 then IP = {addr} LOAD1 - DP1 = {addr} LOAD2 - DP2 = {addr} STORE - Write Acc to data memory using address DP1

Answer 9

LOAD1( with addr n) LOAD2 (with addr m) ADD STORE STOP

Answer 10

cannot use the value in ACC as input so have to store results in memory first Supports smaller selection of instructions LOAD1/2 and JUMP contatin address of DM and IM. so the length of the addr limits max size of DM and IM

Answer 11

used to seperate the execution of the instructions from each other Also used to split single instructions into several parts called fetch-executre

Answer 12

F- Content of IM addressed by IP is fetched into IR D- System decides which register needs new value or which signals needed for IP E - Data registers read thier values from memory and devices of ALU execute their operations. Address of next instruction assigned to IP

Answer 13

input device <---> input module -----> data register output device <------ output module <------ data register

Answer 14

Input-S - write content of dR into memory cell Output-S- write content of memory cell addressed by DP1 into DR of output unit

Answer 15

LOAD1(with= 0) Input-S LOAD1(with=1) Input-S LOAD1(with = 0) LOAD2(with=1) ADD STORE OUTPUT-S STOP

Answer 16

If size of input is unknown, CPU-S(I/O) cannot easily decide whether input has been completly transferred. Every I/O of ALU must pass through memory. Inneficent and slows down data processing

Answer 17

replace data registers with buffer memory so I/O devices can read data independently from current state of CPU

Answer 18

small memory that works in accordance with FIFO principle. Stores data when they become availalbe. Release them when they are needed.

Answer 19

more organised data registers and address registers of I/O unit to Cpu. allowing cpu to directly access content of these registers

Answer 20

uses: keyboard input and output to non-graphical display limits: input can only be read if its expected by programme. It is not possible to interrupt programme by external event.

Answer 21

incase of failure of vital system components Attempt of executing illegal instructions

Answer 22

1. CPU executes programme A 2. if Interrupt recivied, CPU complemets current instruction and then all content of registers in CPU stored in stack area 3. Interrupt handler will be executed. 4 When completed, original content of registers restored and programme A resumes where it stopped.

Answer 23

Vital for efficeient handling of non-programmed input Polling not required

Answer 24

Completion signals external event notifications Allocation of CPU time

Answer 25

Every intterupt given priority 1. Interrupt handler suspends normal programme 2. IH of interrupt 1 suspends IH of interrupt 2 if p(1) > p(2) 3 After completion, next interrupt with highest priority is serviced. if there are several interrupts the n order of occurance decides it.

Answer 26

Using programmed I/o, CPU initiates DMA and sends parameters to I/O modules. 2. The I/O modules can write/read data into/from memory 3. The i/O module sends an interrupt to CPu as completion signal

Answer 27

Sram based on flip-flops so content of memory cells stays unchanged unless changed by new input value DRAM store content in capictors. This content fades away with time and needs to be refreshed every few ms In Sram, read/write operations are very fast while in Dram they are slower In SRAM, number of bits that can be stored on a single memory chip is limited. In DRAM, memory capacity per chip is higher SRAM is expensive as it needs 6 or more transisiotrs for storage of 1 bit. DRAM can store one bit with one capacitor and one tranistor so is rather inexpensive.

Answer 28

if power is removed, then volatile devices lose their content. SUch as cache memory, RAM. if power is removed. then devices keep their content. flash memory. used for permanenet storage/

Answer 29

Memory built from logic gates/capictors(RAM) devices with mechanically moved parts(hdd) semi conductory memory access time is at least 10 times faster than mass storage devices

Answer 30

can be accessed at speeds close to the CPU because of its location. Allowing for programs to be executed more efficiently Another advantage is lower power consuption as accessing cache memory consumes less power compared to main or secondary storage However, due to gate delays and costs, we cannot operate a large cache memory at clock rate of CPU, therefore size is limited. High cost due to cache being typically made from SRAM which is expensive.

Answer 31

1. If instruction are loaded into CPU's registers, the address is first looked up in cache> 2. if not in cache, its looked up in main memory. If found, instructio0n loaded into cache and CPU. 3. If not found in main memory, instructions are loaded for mass storage into cahe and CPU

Answer 32

physical and logical memory addresses. logical address space divided into same size pages split into page address and offset Physical memory is divided into same size frames consisting of frame address and offset When CPU asks for logical address, it's mapped onto physical address which is the position of the actual requested data

Answer 33

Loading data from slower to faster memory When CPU request data not contained in cache, then the content of that particular address along with the full page contating that adress is written to next level of memory hiearchy.

Answer 34

Spatial locality Programmes are organised in a way that often the next address requested by the CPU is very close to the previous one

Answer 35

maps logical addresses onto physical addresses. controls process of writing pages into cache if cache or main memory is full, it determines which page is written back to the next slower level of memory hiearchy using FIFO or least frequently used page. controls data integrity and de and encrypts data

Answer 36

Unidirectional bus - connects two devices with fixed roles.( one device is sender, other device is reciever of data) address bus ad- no agreement necessary between devices about their role Bi directional bus - connects two devices that both can be sender and reciever( data bus and control bus) ad- more flexible regarding number of devices connected

Answer 37

parallel bus - all data travelling at the same time by using n wires in parallel where n corresponds to length of word being transferred. eg. data bus between CPU and memory, ATA bus Serial bus- transfers a word one bit after another. Word is decombosed by sending device and recomposed by revieveing device USB, S-ATA bus

Answer 38

Parallel bus have potetnital of higher data rates as they transfer more than one bit at a time Serial buses faster than parallel buses due to clock rate and distance of parallel data transmission is limited by skew.(bits wont arrive exactly at same time) Parallel buses need more space than serial buses Serial buses preferred for long distance data transfer at high clock rates

Answer 39

point-to-point buses - can connect exactly two deivices eg buses between ALU and CU, AGP bus multipoint- large number of devices use this single bus as common means of exchanging data. PCI, USB

Answer 40

all data have to pass the main bus system of computer

Answer 41

Sender and reciever have the same clock allowoing a constant stream of data to be transmitted

Answer 42

sender and reciver have different clocks p1- the same data are mistakenly read multiple times by reciver if reciver hsa faster clock than sender. p2- some data are missed by reciever, if reciever have slower clock than sender.

Answer 43

stream of data to be transferred, needs to be divided into series of smaller pieces with breaks between transmissions so slower device has time to catch up

Answer 44

SIMPLE SEMI FULL

Answer 45

Daisy chaining method- All devices attached to bus are sequentially connected by a wire for a signal BAV Device can only use bus if it recieves BAV BAV fed into first device in chain(highest priority) If device recieves BAV and does notGee want to use bus, it forwards bav to next device in chain Polling- Bus controller consecutively generates the device addresses of all devices attached to bus This address is forwarded to all devices If a device recognizes its address and wants to use the bus, it blocks the usage for other devices by sending a busy signal to them Independent request- Each device connceted to bus can send request signal to bus controller to use bus bus contorller ranks all request in accordance with a priority and sends grant signal to selected device. Selected device blocks usage of bus fpr pther devices by sending busy signal to them

Answer 46

A general purpose computer is a computer that, given sufficient time and memory, can solve every problem that, in principle, is solvable by a computer

Answer 47

IDC must be modified so that it can decode the new instruction. We need to make sure that the ALU of CPU-S contains a device that can test whether two numbers are identical, Since the instructions of CPU-S have an opcode of 3 bits, we can only encode 2^3 = 8 different instructions. CPU-S already supports 8 instructions, and therefore we have to increase the length of the opcode to 4 bits.

Answer 48

Programmed I/O is always initiated by an instruction and leads to a single word of input from the Input Unit to the CPU or from the CPU to the Output Unit. 2. An interrupt is a non-programmed input of one word into the CPU that leads to a temporary suspension of the programme executed by the CPU and initiates the start of a specific new programme, the so-called interrupt handler. 3. DMA is normally initiated by programmed I/O and leads to a direct transfer of blocks of data from the Input Unit to the Memory Unit or from the Memory Unit to the Output Unit.

Answer 49

1. None. 2. For a memory address of length n in ℕ, the number of directly addressable memory cells equals 2^n.c