Computer Systems Flashcards

(50 cards)

1
Q

Program counter Register

A

Contains address of next instruction to be executed

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2
Q

stack pointer register

A

contains the address of the last executed instruction

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3
Q

Instruciton pointer register

A

contains the addres of the current instruction being executed

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4
Q

accumulator register

A

contrains the results of arithmetic and logic operations

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5
Q

Microprocessor

A

single IC whcih accepts and executes code instructions for data processing and controlling associated comuter circuitry. similar to a CPU

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6
Q

Microcomputer

A

An interconnected group of IC input outputs, mem systems, used for data processing and other applications

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7
Q

microcontroller

A

and integrated system of a single integrated circuit containing microprocessors. IO divides and mem systems.

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8
Q

RHIC

A

reduced instruction set computer simple and iptimized set of instructions

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9
Q

CISC

A

Complex instruciton set computer

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10
Q

ADD R5

A

an example of immediate addressing mode

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11
Q

what does ADD R5 #6 do

A

add the constant 6 to Register 5

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12
Q

what does LOAD R4, (R5) do

A

loads the content in pointer R5 into R4

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13
Q

indirect addressing

A

pointer

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14
Q

immediate addressing

A

constants

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15
Q

direct addressing

A

static data

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16
Q

auto indexed addressing

A

loops

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17
Q

multithreading

A

allows simultaneous execution of multiple threads(subset within a process)

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18
Q

single core processors

A

use time-division multiplexing to provide multiplexing

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19
Q

multicore processors

A

can provide true multithreading without multiplexing

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20
Q

examples of sequential access storage devices

A

cassette tapes, CDs, and DVDs

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21
Q

Flash memory is an example of

A

Random access storage device

22
Q

cache memoryu

A

Low capacity, but very high speed,

used for frequently used data

23
Q

Secondary memory storage device

A

something like a DVD. Nonvolatile and cant be accesed directly by the PC

24
Q

primary memory storage device

A

volatile and can be accessed directly

25
PROM
Programamble read only memory(can be programmed once)
26
EPROM
erasable programmable read-only memory can be erased using UV light.
27
EEPROM
electrically erasable programmable read only memoryu can be erased electrically
28
bit byte and nibble
``` Bit = 1 digit Byte = 8 digits Nibble = 4 digits ```
29
total number of address bits needed for cache memory
depends on total memory totalmem = 2^x x = bits
30
block offset for 512bytes
1. log(2) of 2^9 2. 9 bits is the offset. 512 = 2^9
31
learn calculations in the handout
ok pleb
32
total number of tag bits
tag bits = address bits - index bits - block offset bits
33
RAM
random access memory, typically volotile and loads BIOS on boot
34
ROM
Nonvolatile memory used to store BIOS pre booting of the computer
35
USB
secondary memory device
36
Encryption
data conversion process which prevents unauthorized access.
37
encoding
data transformation process whcih involves changing data format for use in a different system
38
Decoding
the opposite of encoding
39
Hashing
using a hash table to convert a string into a much smaller unique representaiton
40
computer architecture
describes teh logical and fx design of a computer syutem including its instruction sets, registers, addressing mode, etc. HIGH LEVEL issues
41
computer organization
deals with low level issuyes, talks about structure and connection of various components
42
CPU
central processing unit - responsible for decoding and executing instructions cosnists of ALU and CU and registers set array
43
ALU
arithmetic logic unit, does adding subtracting and other stuff
44
CU
control unit coordinates operations between ALU and memory and other stuff
45
registers
used for super small and fast data memory
46
BUS
provides communication path between CPU and peripheral devices
47
DATA BUSq
bidirectional bus carrying data/instructions between CPU and peripheral devices.
48
ADDRESS bus
allows CPU to address memory locations, unidirectional and only carries addresses.
49
control Bus
bidirectional bus that carries primary command/control timing signals
50
width of a data bus
determines the amount of data transferred per unit time | wider = more data.