Design Basics in Digital Logic Design

Question 1

Clock Gating

Answer 1

Conditionally (called Gating Condition) enabling and disabling of the clock
if gating condition met, clock is enabled otherwise disabled

Question 2

in clock gating…

Answer 2

an additional clock enable signal is introduced for specific functional blocks, i.e. depending on the signal on clock enable, it will be decided whether the clock signal should pass through those functional blocks.