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What is the general structure of CMOS logic

A pull-up network in series with a pull-down network


How are the PUN and PDN related?

They are complimented variables. PDN=nY PUN=Y
One can be found from the other by DeMorgan's thereom or the duality property.


What is the duality property in CMOS?

For combinational logic, Where a series branch exists in one, a parallel branch exists in the other.