E7 - PRACTICAL CIRCUITS [8 Exam Questions - 8 Groups] 108 Questions Flashcards
“Which circuit is bistable?”
A. An AND gate
B. An OR gate
C. A flip-flop
D. A bipolar amplifier
C. A flip-flop
“What is the function of a decade counter?”
A. It produces one output pulse for every 10 input pulses
B. It decodes a decimal number for display on a seven-segment LED display
C. It produces 10 output pulses for every input pulse
D. It decodes a binary number for display on a seven-segment LED display
A. It produces one output pulse for every 10 input pulses
“Which of the following can divide the frequency of a pulse train by 2?”
A. An XOR gate
B. A flip-flop
C. An OR gate
D. A multiplexer
B. A flip-flop
“How many flip-flops are required to divide a signal frequency by 4?”
A. 1
B. 2
C. 4
D. 8
B. 2
“Which of the following is a circuit that continuously alternates between two states without an external clock?”
A. Monostable multivibrator
B. J-K flip-flop
C. T flip-flop
D. Astable multivibrator
D. Astable multivibrator
“What is a characteristic of a monostable multivibrator?”
A. It switches momentarily to the opposite binary state and then returns to its original state after a set time
B. It produces a continuous square wave oscillating between 1 and 0
C. It stores one bit of data in either a 0 or 1 state
D. It maintains a constant output voltage, regardless of variations in the input voltage
A. It switches momentarily to the opposite binary state and then returns to its original state after a set time
“What logical operation does a NAND gate perform?”
A. It produces logic 0 at its output only when all inputs are logic 0
B. It produces logic 1 at its output only when all inputs are logic 1
C. It produces logic 0 at its output if some but not all inputs are logic 1
D. It produces logic 0 at its output only when all inputs are logic 1
D. It produces logic 0 at its output only when all inputs are logic 1
“What logical operation does an OR gate perform?”
A. It produces logic 1 at its output if any or all inputs are logic 1
B. It produces logic 0 at its output if all inputs are logic 1
C. It only produces logic 0 at its output when all inputs are logic 1
D. It produces logic 1 at its output if all inputs are logic 0
A. It produces logic 1 at its output if any or all inputs are logic 1
“What logical operation is performed by an exclusive NOR gate?”
A. It produces logic 0 at its output only if all inputs are logic 0
B. It produces logic 1 at its output only if all inputs are logic 1
C. It produces logic 0 at its output if only one input is logic 1
D. It produces logic 1 at its output if only one input is logic 1
C. It produces logic 0 at its output if only one input is logic 1
“What is a truth table?”
A. A table of logic symbols that indicate the high logic states of an op-amp
B. A diagram showing logic states when the digital device output is true
C. A list of inputs and corresponding outputs for a digital device
D. A table of logic symbols that indicate the logic states of an op-amp
C. A list of inputs and corresponding outputs for a digital device
“What type of logic defines “1” as a high voltage?”
A. Reverse Logic
B. Assertive Logic
C. Negative logic
D. Positive Logic
D. Positive Logic
“For what portion of the signal cycle does each active element in a push-pull Class AB amplifier conduct?”
A. More than 180 degrees but less than 360 degrees
B. Exactly 180 degrees
C. The entire cycle
D. Less than 180 degrees
A. More than 180 degrees but less than 360 degrees
“What is a Class D amplifier?”
A. A type of amplifier that uses switching technology to achieve high efficiency
B. A low power amplifier that uses a differential amplifier for improved linearity
C. An amplifier that uses drift-mode FETs for high efficiency
D. A frequency doubling amplifier
A. A type of amplifier that uses switching technology to achieve high efficiency
“Which of the following components form the output of a class D amplifier circuit?”
A. A low-pass filter to remove switching signal components
B. A high-pass filter to compensate for low gain at low frequencies
C. A matched load resistor to prevent damage by switching transients
D. A temperature compensating load resistor to improve linearity
A. A low-pass filter to remove switching signal components
“Where on the load line of a Class A common emitter amplifier would bias normally be set?”
A. Approximately halfway between saturation and cutoff
B. Where the load line intersects the voltage axis
C. At a point where the bias resistor equals the load resistor
D. At a point where the load line intersects the zero bias current curve
A. Approximately halfway between saturation and cutoff
“What can be done to prevent unwanted oscillations in an RF power amplifier?”
A. Tune the stage for maximum SWR
B. Tune both the input and output for maximum power
C. Install parasitic suppressors and/or neutralize the stage
D. Use a phase inverter in the output filter
C. Install parasitic suppressors and/or neutralize the stage
“Which of the following amplifier types reduces even-order harmonics?”
A. Push-push
B. Push-pull
C. Class C
D. Class AB
B. Push-pull
“Which of the following is a likely result when a Class C amplifier is used to amplify a single-sideband phone signal?”
A. Reduced intermodulation products
B. Increased overall intelligibility
C. Signal inversion
D. Signal distortion and excessive bandwidth
D. Signal distortion and excessive bandwidth
“How can an RF power amplifier be neutralized?”
A. By increasing the driving power
B. By reducing the driving power
C. By feeding a 180-degree out-of-phase portion of the output back to the input
D. By feeding an in-phase component of the output back to the input
C. By feeding a 180-degree out-of-phase portion of the output back to the input
“Which of the following describes how the loading and tuning capacitors are to be adjusted when tuning a vacuum tube RF power amplifier that employs a Pi-network output circuit?”
A. The loading capacitor is set to maximum capacitance and the tuning capacitor is adjusted for minimum allowable plate current
B. The tuning capacitor is set to maximum capacitance and the loading capacitor is adjusted for minimum plate permissible current
C. The loading capacitor is adjusted to minimum plate current while alternately adjusting the tuning capacitor for maximum allowable plate current
D. The tuning capacitor is adjusted for minimum plate current, and the loading capacitor is adjusted for maximum permissible plate current
D. The tuning capacitor is adjusted for minimum plate current, and the loading capacitor is adjusted for maximum permissible plate current
“In Figure E7-1, what is the purpose of R1 and R2?”
A. Load resistors
B. Voltage divider bias
C. Self bias
D. Feedback
B. Voltage divider bias
“In Figure E7-1, what is the purpose of R3?”
A. Fixed bias
B. Emitter bypass
C. Output load resistor
D. Self bias
D. Self bias
“What type of amplifier circuit is shown in Figure E7-1?”
A. Common base
B. Common collector
C. Common emitter
D. Emitter follower
C. Common emitter
“Which of the following describes an emitter follower (or common collector) amplifier?”
A. A two-transistor amplifier with the emitters sharing a common bias resistor
B. A differential amplifier with both inputs fed to the emitter of the input transistor
C. An OR circuit with only one emitter used for output
D. An amplifier with a low impedance output that follows the base input voltage
D. An amplifier with a low impedance output that follows the base input voltage