ECE 368 EXAM 1 Chris Edition Flashcards
(178 cards)
1
Q
How do you convert a binary number to two’s compliment (assuming a negative value is desired)?
A
Change all 0’s to 1’s and all 1’s to 0’s, then add 1 to the final result
2
Q
How do you convert a binary number to a hexadecimal number?
A
Take groups of four bits starting from the right of the binary number and transform them to the corresponding.
3
Q
How do you convert a binary number to one’s compliment (assuming a negative value is desired)?
A
Change all 0’s to 1’s and all 1’s to 0’s
4
Q
What does VHDL stand for?
A
VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language
5
Q
What is the main purpose for using VHDL?
A
Circuit synthesis and implementation with an FPGA
6
Q
What is synthesis in VHDL?
A
The translation of source code into a hardware
structure that implements the intended functionality
7
Q
What is simulation in VHDL
A
A testing procedure to ensure that such
functionality is indeed achieved by the synthesized circuit
8
Q
Are all constructs in VHDL able to be simulated?
A
Yes
9
Q
Are all constructs in VHDL able to be synthesized?
A
No
10
Q
Are statements in VHDL (With exception of process) executed in parallel or series?
A
Parallel
11
Q
Is VHDL case sensitive?
A
No (With a single exception)
12
Q
How do you trigger comments in VHDL?
A
By using a ‘- -‘ (Double dash)
13
Q
How do you terminate a statement in VHDL?
A
By using a ‘;’
14
Q
Identifiers in VHDL must always start with:
A
An alphabetic letter
15
Q
Identifiers in VHDL can contain:
A
Letters, digits, and the ‘_’ character
16
Q
Can a VHDL identifier end with ‘_’?
A
No
17
Q
Can a VHDL identifier contain successive ‘_’ characters (ex: ‘__’) ?
A
No
18
Q
Are the following identifiers valid?
1) A
2) X0
3) last@value
4) Next_Value
5) 5bit_counter
6) _A0
7 ) A0_
8) Clock__Pulse
A
1) Yes
2) Yes
3) No (Can’t have ‘@’)
4) Yes
5) No (Can’t start with ‘5’)
6) No (Can’t start with ‘_’)
7) No (Can’t end with ‘_’)
8) No (Can’t contain '__’)
19
Q
What are the 3 fundamental VHDL code sections?
A
1) Library Declarations
2) Entity
3) Architecture
20
Q
What does the Library Declarations section of VHDL code consist of?
A
Lists all libraries and respective packages needed in the design
21
Q
What does the Entity section of VHDL code consist of?
A
Specifies the I/O ports of the circuit, plus (optional) generic constants
22
Q
What does the Architecture section of VHDL code consist of?
A
Describes how the circuit behaves, from which a compliant hardware is inferred.
23
Q
What are the three different VHDL architectures?
A
1) Structural
2) Behavioral
3) Dataflow
24
Q
How does the dataflow architecture work?
A
Describes how the data flows from the inputs to the output most often using NOT, AND and OR operations.
25
Structural VHDL allows the designer to represent a system in terms of ______________ and their ______________.
1) Components
2) Interconnections
26
(T/F) Structural descriptions can show a more concrete relation between code and physical hardware.
True
27
(T/F) Behavioral descriptions show interconnections at any level of abstraction.
False (This would be true if Behavioral were replaced by Structural)
28
In structural architecture, how are components interconnected?
With the use of signals
29
In structural architecture, how are components declared? (Obvious answer)
With component declarations
30
In structural architecture, how are components instantiated? (OBVIOUS ASS ANSWER)
With component instantiation statements
31
What is component declaration in structural VHDL?
Defines kind of module used, specifies external interface
to component in terms of generic constants and ports.
32
(T/F) A different name for the component in comparison to the entity of the component module is used for component declaration
False (The same name is used)
33
(T/F) Component declaration uses the same port declaration as a module entity declared as component
True
34
(T/F) Component declaration is outside architecture body with signal declaration
False (Inside the architecture body, just before the 'BEGIN')
35
(T/F) Component instantiation is located outside architecture body
False (Inside the architecture body, just after the 'BEGIN')
36
What is component instantiation?
Specifies usage of module in design
37
What are the two ways ports can be assigned?
1) By name
2) By position
38
(T/F) Order is not important when assigning ports by position
False (Position is crucial)
39
How do you assign ports by name in VHDL (Syntax)?
Name_of_component_port => Entity_Port_name_or_signal
40
(T/F) The order of component ports is explicitly assumed to be the same as in component declaration
True
41
Are \clk\, \CLK\, and \Clk\ considered different names/identifiers?
Yes (VHDL is not case sensitive only when identifier surrounded by backslashes)
42
Is arch a reserved VHDL word?
No
43
What is an identifier used for in VHDL?
They are used to name VHDL items such as signals, variables, entity declarations, etc.
44
What delimiter is used to assign a value to a signal?
<=
45
What delimiter is used to assign a value to a variable, constant, and initial value of a signal?
:=
46
How many bits does the type integer operate with?
Up to 32 bits
47
(T/F) Xnor is a reserved VHDL word
True
48
(T/F) a delimiter with one character is referred to as a compound delimiter.
False (This is a simple delimiter)
49
How many synthesizable characters are there in VHDL?
256
50
(T/F) Single quotes indicate a single character/bit whereas double quotes indicate a string of characters/bits
True
51
(T/F) Component is a VHDL reserved word
True
52
(T/F) The ".all" extension makes all elements of a certain package visible
True
53
What is an object in VHDL?
An object is a named item of a specific type that has a
value of said type.
54
What are the four VHDL objects?
1) Signal
2) Variable
3) Constant
4) File
55
(T/F) Objects declared in a process are available to all VHDL descriptions
False (Only available to within process)
56
(T/F) Objects declared in an entity are available to all
architectures associated with that entity
True
57
(T/F) Objects declared in an architecture are available to all statements in the entity
False (Only available within the scope of the architecture)
58
(T/F) Objects declared in an entity are available to all
architectures associated with that entity as well as the architecture
False (Only available within the scope of the entity)
59
What is a constant in VHDL?
An object whose value can not be changed
Syntax: CONSTANT constant_name: constant_type := constant_value;
60
What VHDL type can a constant be?
Any!!!
61
What is a deferred constant?
A constant declared without its value
62
What does the keyword others help to accomplish?
Represents all index value that were left unspecified
Syntax Example: CONSTANT b: BIT_VECTOR(7 DOWNTO 0) := (7 => ‘0’, OTHERS => ‘1’)
63
What is a signal in VHDL?
An object that passes values in and out of the circuit, as well as between its internal units (i.e a wire).
Syntax: SIGNAL signal_name: signal_type[range] [:= default_value];
64
Are signal declarations allowed in sequential code?
FOOO
65
Can signals be used in sequential code?
Yes
66
(T/F) All ports of an entity are constants by default
False (Signals)
67
(T/F) Default values for signals is recommended in code that is for synthesis
False (Not recommended in synthesis code)
68
What is a variable in VHDL?
An object that represents local information
Syntax: VARIABLE variable_name: variable_type[range] [:= default_value];
69
Name the 10 synthesizable data types from standard package
1) BIT
2) BIT_VECTOR
3) BOOLEAN
4) BOOLEAN_VECTOR
5) INTEGER
6) NATURAL
7) POSITIVE
8) INTEGER_VECTOR
9) CHARACTER
10) STRING
70
(T/F) A scalar type is declared using the keyword type.
True
Syntax: type type_name is type_definition
71
(T/F) An array type is declared using the keyword type and vector.
False (vector should be array)
Syntax: type type_name is array (range_spec) of base_type_name [range_spec]
72
What is a subtype in VHDL?
A subtype is a type with a constraint
73
(T/F) Type Bit can either be TRUE or FALSE
False (Either '1' or '0')
74
(T/F) Type Bit supports logic operations (OR, AND, etc.)
True
75
What is a bit vector in VHDL (Yes its as obvious as you think)
A vector of bits (Told you)
76
What four operations does a bit vector support?
1) Logical
2) Comparison
3) Shift
4) Concatenation
77
(T/F) For logical and shift operations, the vectors are required to have half the length of the output signal.
False (Lengths must be the same)
78
What two values can type Boolean be?
True and False
79
(T/F) The Boolean vector supports the same four operations as a bit vector (Logical, Comparison, Shift, and Concatenation)
True
80
(T/F) The actual bounds are referred to as INTEGER’LOW (on the left) and INTEGER’HIGH (on the right)
True
81
(T/F) Natural is a subtype of Boolean
False (It is a subtype of integer)
82
(T/F) Natural is a subtype of bit
False (It is a subtype of integer)
83
What two operations does the integer type support?
1) Arithmetic
2) Comparison
84
What operator does type character support?
Comparison
85
How many bits are required to represent a character?
8 bits (1 byte)
86
(T/F) A string is an array type of character
True
87
What are the nine values type std_logic can take on?
1) 'X' (Forced unknown)
2) '0' (Forced low)
3) '1' (Forced High)
4) 'Z' (High Impedance)
5) 'W' (Weak unknown)
6) 'L' (Weak low)
7) 'H' (Weak high)
8) '/-' (Don't care)
9) 'U' (Unresolved)
88
What are three benefits of using a tri-state buffer?
1) Artificially create delay
2) Increase current fed to other devices
3) Controls what devices are able to access a data bus
89
(T/F) High impedance circuits are high current, low voltage (A wire)
False (High voltage, low current (An open))
90
What is the output for a Tri-state buffer when the control is low? What is the output for a Tri-state buffer when the control is high?
1) High impedance (Z)
2) The value seen at the input
91
(T/F) STD_ULOGIC is a subtype of STD_LOGIC
False (STD_LOGIC is a subtype of STD_ULOGIC)
92
(T/F) STD_LOGIC_VECTOR is a subtype of STD_ULOGIC_VECTOR
FALSE (BACKWARDS)
93
What are the types signed and unsigned subtypes of?
std_logic
94
What are the types fixed and float subtypes of?
std_logic
95
LEGAL OR ILLEGAL
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR (7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
1) a <= b(5);
2) b(0) <= a;
3) c <= d(5);
4) d(0) <= c;
5) a <= c;
6) b <= d;
7) e <= b;
8) e <= d;
1) LEGAL
2) LEGAL
3) LEGAL
4) LEGAL
5) ILLEGAL (TYPE MISMATCH)
6) ILLEGAL (TYPE MISMATCH)
7) ILLEGAL (TYPE MISMATCH)
8) ILLEGAL (TYPE MISMATCH)
96
What is the identifier used for data concatenation?
&
97
(T/F) When aggregating data, the others keyword must come first
False (Must come last)
EX: ('1', '1', others => '0')
98
(T/F) Concatenation of aggregates is legal
True
99
(T/F) Parenthesis are mandatory for concatenation
False (Optional)
100
(T/F) Parenthesis are mandatory for data aggregation
True
101
What does the resize function do?
It is used to extend or reduce the size of arrays
102
How is an unsigned extension performed?
Append '0' to front of vector until ideal size reached
103
How is an unsigned reduction performed?
Remove frontmost bits until ideal size reached
104
How is a signed extension performed?
Append sign bit to front of vector until ideal size reached
105
How is a signed reduction performed?
Keep frontmost bit as sign bit, then remove bits afterwards until ideal size reached
106
What are the three types of type conversions?
1) Automatic
2) Type Cast
3) Type-conversion function
107
What is the purpose of behavioral architecture in VHDL
To show the output is derived from the inputs using
structured statements
108
What are the two types of statements for behavioral architecture?
1) Concurrent
2) Sequential
109
What type of circuits are concurrent statements useful for?
Combinational circuits
110
What is combinational logic?
When the output only depends on the current input (No memory)
111
What are the three purely concurrent statements?
WHEN,SELECT, GENERATE
WHEN EX: y <= “00” WHEN (a AND b) = “01” ELSE
“11” WHEN (a AND b) = “10” ELSE
“ZZ”; -- high impedance
SELECT EX: WITH identifier SELECT
assignment_expression WHEN values,
assignment_value WHEN values,
……;
112
Does the when statement require all outputs to be specified?
No, but it is recommended
113
What does the unaffected keyword do?
It keeps the state of the signal the same
114
(T/F) Multiple values are accepted in SELECT statement, which can only be grouped with “|” or “TO”
True
115
(T/F) The SELECT statement requires that all input values be covered
True
116
(T/F) The generate statement is analogous to that of a sequential loop statement
True
117
What are the two types of generate statements?
1) Conditional
2) Unconditional
118
What is the FOR-GENERATE used for?
To create multiple instances of a section of code
119
(T/F) Range for generate statements is required to be dynamic
False (Static)
120
Where is a generic declared?
Before the port in the entity
121
(T/F) Generics are truly global
True
122
Are generics constant?
Yes
123
Are generics synthesizable?
Yes
124
What is the => operator used for?
Assigning values to array elements
125
What is the := operator used for?
Assigning values to a variable, constant, and initializing a signal
126
What is the <= operator used for?
Assigning values to a signal
127
(T/F) All logical operators have equal precedence
False (NOT has higher precedence)
128
What are the seven logical operators in VHDL?
1) NOT
2) OR
3) NOR
4) AND
5) NAND
6) XOR
7) XNOR
129
(T/F) Parenthesis can be used to control precedence of logical operators
True
130
Do unary operators take an operand from the left or right?
Right
131
Do binary operators take an operand from the left or right?
Both (TRICK QUESTION LOL)
132
abs(x) returns:
The absolute value of x
133
x REM y returns:
Remainder of x/y with sign of x
134
x MOD y returns:
Remainder of x/y with sign of y
135
What are the eight arithmetic operators?
1) + (add)
2) - (Subtract)
3) * (Multiply)
4) / (Divide)
5) ** (Exponentiation)
6) ABS (Absolute value)
7) REM (Remainder)
8) MOD (Modulo)
136
What are the six comparison operators?
1) Equals to (=)
2) Not equal (/=)
3) Less than (<)
4) Greater than (>)
5) Less than or equal (<=)
6) Greater than or equal (>=)
137
(T/F) The synthesizable predefined data types that support comparison operators are BIT, BIT_VECTOR, BOOLEAN, INTEGER, NATURAL, POSITIVE, CHARACTER, and STRING
True
138
Can bit vectors of different lengths be equal
No, different sized bit vectors never equal
139
What happens when doing comparisons of two differently sized bit vectors (Not including equal or unequal)
Leftmost bits of longer vector discarded
140
(T/F) When doing comparisons of bit vectors (Not including equal or unequal), if the vectors being compared become equal, the longer vector is considered larger than the other.
True
141
For all other SU-based types (not bit vector), are different sized vectors allowed in comparisons?
Yes
142
For all other SU-based types (not bit vector), what happens when the vectors are different sizes?
The shorter vector is resized to the length of the longer vector
143
What are the six shift operators in VHDL?
1) Shift left logic (SLL): positions on the right are filled with ‘0’s
2) Shift right logic (SRL) : positions on the left are filled with ‘0’s
3) Shift left arithmetic (SLA): rightmost bit is replicated on the right.
4) Shift right arithmetic (SRA): leftmost bit is replicated on the left
5) Rotate left (ROL): circular shift to the left
6) Rotate right (ROR): circular shift to the right
144
x = “01001”
1) y <= x SLL 2;
2) y <= x SLA 2;
3) y <= x SRL 3;
4) y <= x SRA 3;
5) y <= x ROL 2;
6) y <= x SRL -2;
1) "00100"
2) "00111"
3) "00001"
4) "00001"
5) "00101"
6) "00100"
145
(T/F) Reduction operators perform the binary logical operation on each individual bit in the string
True
146
What does T'Ascending return?
True if elements in T are in ascending order
147
What does T'Left return?
Leftmost value of T
148
What does T'POS(X) return?
Position number of X as an integer
149
What does T'RIGHTOF(x) return?
Value on the right of the position number X in T
150
(T/F) Predefined attributes can be applied to matrix types
True
151
(T/F) Data types can not be defined by the user
False
Syntax: TYPE type_name IS RANGE range_specifications;
or
TYPE type_name IS (type_values_list);
or
TYPE type_name IS ARRAY (range_specs) OF element_type;
152
How do you index a 1D x 1D array?
(x)(y) (x and y any integer index)
153
How do you index a 2D array?
(x, y) (x and y any integer index)
154
How do you index a 1D x 1D x 1D array?
(x)(y)(z) (x, y, and z any integer index)
155
How do you index a 3D array?
(x, y, z) (x, y, and z any integer index)
156
What are the main official VHDL packages?
"std"
"ieee"
157
How many packages are in the main official VHDL libraries?
Three in "std".
Twelve in "ieee".
158
What is one of the most important packages in VHDL? what does it do?
from the ieee library: "std_logic_1164".
defines the nine-value type std_ulogic, and std_ulogic_vector.
159
How do you make a package visible to the compilier?
Declare it with library and use clauses.
library library_name;
use library_name. package_name. all;
160
What clauses are introduced automatically in VHDL projects?
library "std", "work";
use std.standard.all;
161
What are the most frequently used packages and libraries?
Package "standard" from the "std "library.
Library "work"
Package "std_logic/_1164", from the "ieee" library
Package "numeric/_std", from the "ieee" library
162
where is the "textio" package from and what is it used for?
from the library "std"
For dealing with text and files.
163
where is the "env" package from and what is it used for?
from the library "std"
For communication with the simulation environment.
164
What package can implement both fixed point and floating point arithmetic circuits?
Library ieee "fixed_float_types"
165
what does the package "numeric_bit" do
Introduces the types signed and unsigned and corresponding operators with bit as base type.
166
What does the package "numeric_bit_unsigned" do?
Package numeric_bit_unsigned: Contains operators and other functions for type bit_vector.
167
What does the package "numeric_bit_unsigned" do?
Package numeric_bit_unsigned: Contains operators and other functions for type bit_vector.
168
What library declaration do you use for arithmetic functions with Signed or Unsigned values?
"IEEE.NUMERIC_STD.ALL"
169
What does the package "Fixed_generic_pkg" do?
Defines the unsigned and signed fixed-point types ufixed and
sfixed, respectively,
170
What does the package "standard" do?
For implementing all sorts of logic and integer based arithmetic circuits but with major limitations; not recommended for arithmetic circuits and circuit ports
171
What does the package "std_logic_1164" do?
For Implementing any logic or arithmetic circuit (for the latter,
must associate with another package, like #7, #10, or #13)
172
What does the package "numeric_bit" do?
For implementing integer arithmetic circuits with type
unsigned or signed; has bit as base type
173
What does the package "numeric_std" do?
For implementing integer arithmetic circuits with type
unsigned or signed; has std_ulogic as base type
174
What does the package "numeric_bit_unsigned" do?
For doing unsigned operations with type bit_ vector
175
What does the package "numeric_std_unsigned" do?
For doing unsigned operations with type std_ulogic_vector
176
What does the packages "fixed_pkg", "fixed_generic_pkg", and "fixed_float_types" do?
For implementing fixed-point arithmetic circuits
177
What does the packages "fixed_float_types", "float_pkg", and "float_generic_pkg" do?
For implementing floating-point arithmetic circuits
178
What does the package "math_real" do?
For determining generic parameters (support not required for
synthesis, but might exist for real values that are static)
