Electronics Flashcards

Question

A*(A+B)=

Answer 1

(A+B)' = A' *B' A'*B' = A' +B' The negation (NOT) of a disjunction (OR) is the conjunction (AND) of the negations. * The negation of a conjunction is the disjunction of the negations

Answer 2

A (XOR) B = AB' + A'B

Answer 3

(A(XOR)B)'

Answer 4

inverter with 2 swithc in series to ground - input - means not connected - input 1 - means connected THe switched wire goes to a node where it is parallel - V out and Vs (resistor) So basically only goes to ground if 11

Answer 5

We have a switch to ground - But replace the switch with transistor so its V+ resistor then node in paralle l to vo OUT or to aour transistor to ground SO if we have signal on - the transistor conducts and we go to ground - low state if we are not coducting - the transistor doesnt conduct goes to v0 high state

Answer 6

So this is our not gate BUT instead of just a plain voltage input going in we have 2 inputs A and B in parallel - each has a diode before they join - and they join and go to the base

Answer 7

High level is VOH - VIH low level is VIL - VOL note IH is input high IL is input Low OH is output high OL is output Low

Answer 8

the time ti takes to swithc or for a transisitor to function We have rise time and fall time in the circuit Propogation time is the average of the two swtiching times measured at 50% point (so time from start of switch to 50% point) TPHL and TPLH

Answer 9

so If we have a BJT - not analog circuit when the transistor conducts - our output voltage is brought down to SATURATION voltage 0.2 (this means the transisitor is saturated (so not all voltage goes to ground I guess - depending on saturation of transistor) Being saturated however means we have excress charge on the base region (makes sense - once you reach a certain level of base voltage (saturation) you aren't conducting any extra) This excess charge at the bease means it TAKES LONGER to turn off the device - this extra time to dissipate charge at the base is called STORAGE TIME so faster to turn on then turn off

Answer 10

We use a SHOTTKY DIODE - It prevents saturation of the transistor (thus doesnt take as long to turn off) it does this by having another wire from the base going to the collector with our SHOTTKY diode on it (so one way) - has a very low voltage drop so shunts the excess current to the collector

Answer 11

Static - I^2R - passively Dynamic - I^2R due to charging and disrcharging through resistances

Answer 12

the power it takes to turn off and on our logic gate - performance factor to compare logic families calculate PDP as tPD *power dissipation (propogation times power dissipation)

Answer 13

) Symbol for an inverter operating with power supplies of 0 V and V+. (b) Simple inverter circuit comprising a load resistor and switch. (c) Inverter with NMOS transistor switch. (d) Inverter with BJT switch

Answer 14

TTL, CMOS and ECL TTL is transisitor transistor logic CMOS is complementary metal oxide semiconductor ECL is emitter coupled logic ECL sucks

Answer 15

CMOS - low power consumption - using ina ll microcomputer chips (so can put a ton of them together and not so much heat) can be damaged by static TTL- most rugged least susceptible to electric damage, COnsumer more power not suitable for battery power ECL- fast - uses more power and careful wiring

Answer 16

connect BJTs together to make TTL we connect NMOS andPMOS to make CMOS

Answer 17

noise immunity is the idea that we can tolerate noise and still have fidelity of 1's and 0s - an in between signal is properly shunted to 0 or 1 eg 5 - 2.5 is 1 0 - 2.5 is 0

Answer 18

Noise margis are the differences between what we allow our High input value to be vs what the Hihg output is (see the low as well) so for example can input 2.8 and thats within Input High and will only output between 4.8-5 for output high

Answer 19

its a metal - with a junction then N type silicon - -very small junction the voltage drop is very small compared to normal diode because of this 0.25 vs 0.6

Answer 20

fan in - # of inputs to a gate fan out is the ability of the output of one gate to drive subsequent gates (eg can the output of this one gate go into 8 other gates after - typically can do 10)

Answer 21

Current source is one gate driving another - so the I OH (current of output High ) or the current of output low Similarly Current sink is the opposite - Current of input HIgh or current of input Low - can the incoming current drive our gate

Answer 22

Ratio of output and input current min(Ioh/Iih ; Iol/IIl) note there is a fanout high and a fanout low overall fan out is whicher is lower

Answer 23

7400 - basic 74S00 - shottky 74LS00 - low power shottkey

Answer 24

1-1/6 voltes - tyically operated from 5 V supply

Answer 25

Small ,medium ,large -basically how many gates small is less than 12 medium is 12-100 etc TTL is used for small and medium - more would be CMOS?

Answer 26

Manufactourer code specification Family Membrer

Answer 27

NAND has multiple emitter - Nor has 2 separate transisitors

Answer 28

If two totem poles are connected - its excessive high current - causes damage so to prevent that remove the active pull up transistor so use an open collector - only acts as current sink - only drive output of low and only work when connected to pull up resistor ALLOWS FOR WIRED-AND! (allows gates to be connected) So the idea is our gates are connected to common pull up resistor and any gate can make the signal line low - only output high if all high (AND GATE)

Answer 29

For NMOS - source pointing to gaet - for PMOS gate pointing to source NMOS - turn on with Vgs>0 Gate >0 for Pmos - to turn on with Voltage Less than 0

Answer 30

in CMOS - use a pair of 1 NMOS and 1 PMOS - and the combined drain is Vout

Answer 31

can't forward bias both of them so cant both draw current no current consumed at steady state (besides leak) large noise margin

Answer 32

COMBINATIONAL (memoryless ) - functions only present values of inputs SEQUENTIAL - compute output based on inputs and STATE (memory)

Answer 33

flip flops 0- basic building blod sequential logic circuits - build up memory so any circuit with 2 outputs - each that has 2 stable logic level - hi and low also determined by a clock - clock edge determines when new bit enters

Answer 34

essentialy 2 nand gates but the output of each becomes an input for the other S means set and R means reset (set means output 1 reset means output 0)'output is lathed so SR -FF called gated Not only change when S or R goes from 1 to 0 not 0 to 1

Answer 35

can never be 00, 01 and 10 makes data output 11 is NC - data storage - its a hold because doing from 0 to 1 is not a change Draw timing diagram ACTIVELY LOW - when S bar goes to 0 swets a TO 1 wHEN r GOES TO 0 SETS q TO 0

Answer 36

active high - so when S set to 1 sets Q to 1 when R set to 1 set q to 0 (activate on leading edge

Answer 37

has inputs for clock - so clock needs to be 1 for changes to occur - if 0 no changes occur - others works as normal NAND or NRO sr flip flop NOTE - S and R here are one step before Sbar and R bar so now for our NAND gate - to switch we need clock enabled - and S to go to 0-> 1 or R- to be 0->1 SO S 1 and clock 1 sets Q to high and need clock 1 and R 1 to reset it down

Answer 38

Its essentially the clock NAND flipflop BUT instead of two separate R and S inputs - there's just one Data input - becomes S and Data -> not -> R and then Clock with S and R NAND becomes S' and R' again so can make table with this and timing table so when D on its like S is on so clock on D on means Q is up but C on and D down is like R so Q goes down So called PUSLE TRIGGER - output collows any input change in D as long as c = 1

Answer 39

So this is a data pulse flip flop but instead the not is on the clock so Data goes in and clock goes into NOT - into first box to make Q and the output of that has one as is and the other NOT (to make our flipped S and R) goes into another box each output one to one with S and R but the clock now takes initial clock input (not inverted) So now Q only shifts to high when clock is changing from 0-1 (edge trigger) AND D is 1

Answer 40

So nand gate - J and K - clock goes into both - each output from NAND goes into our NAND flipflop Key indifference is that our initial NAND actually has 3 inputs and is feedback into by the opposite result at the very end this allows for all 4 possible combos of J and K So for Q to change - changes on Clock rising edge 1 and a J of 1 sets it to high and a K of high sets it back down

Answer 41

data storage, counters etc

Answer 42

Ripple (asynchronous) - flip flop output serves as source for triggering other flipflops Synchronous - all flip flops triggered by same clock signal

Answer 43

So the output of one flipflock - becomes the clock for another so basically like a ripple for synchronous all the same clock Negative edge counter - works as N bit counter - basically as you move down the FF's they have larger lengths of time they're on or that they osciallate between on and off

Answer 44

put counters in arbitrary state determine output use new input to determine next state set up next form current

Answer 45

It is impossible to forward bias both MOSFETs simultaneously to draw current from the power supply. * No power is consumed at the steady states (except ~10nW due to leakage current) regardless of the logic state of input. * Other advantages include larger noise margin, better immunity to temperature fluctuation, large fan-out capability

Answer 46

Pull down acts as current sink - at low output - pulsl voltage down to ground - so from output its below it and pulls current down Pull up - acts as current source - when high output - this is the one right above out output and its current sourcing or pull up - send the current down into output

Answer 47

so its going to be our TTL gate WITHOUT a pull up resistor sso only pull down (only current sink) - which basically means always high unless we are pulling down this allows for WRIING AND - So each individual gate does not have a pull up but there is ONE COMMON pullup for all of them -any collector pulls the line low but the output is high only when they are all high - that's why its WIRED AND (conversely wired or is when all connected to a common pull down)

Answer 48

Basically when either S or R goes from 1 to 0 they;re behaviour occurs (set or reset) (set making Q 1 and reset making Q 0 - states can be 1 , 0; 0, 1 or 11 (No change - hold( - can never be 00 OK this makes sense starting with zero because anand gate with a - input HAS to be 1

Answer 49

0 0 is hold, from 0 -1 causes our action 0->1 on S makes Q = 1 never 1 1

Answer 50

So SR NAND gflip flop BUT - have clock at start clock goes into and with S and R and these make S and R prime and we read S and R prime like a normal SR flip flop (so 11 set not change, 1 0 means reset and 0 1 means set) and no 00 to draw start with clock at 0 the move to 1 then try all the combos of R and S keeping in mind starting with 0 gets you rresults

Answer 51

so same idea as clock flip flop but S and R represented by D data - and data makes S and R opposite by nature (one is a not) so can never have a set state - if clock is up - either data state makes a change (set or reset) - called PUSLE trigger

Answer 52

SR NAND SR NOR Clocked SR NAND Pulse trigger SR NAND edge trigger JK flipflop

Answer 53

so 0 0 - no change 1 0 makes 1 0 1 makes 0 but 11 is toggle as in every clock goes back and forth!! key for writing out the output

Answer 54

Set counter up abritrarily set up inputs then do outputs and keep going as counter moves up