Embedded Interview Prep Flashcards
(47 cards)
What is the difference between a microcontroller and a microprocessor?
An MCU integrates CPU, memory, and peripherals on one chip for dedicated control (e.g. ATmega328P, STM32F4). An MPU is just a CPU core requiring external memory and I/O, optimized for high-performance OS tasks (e.g. Intel Core i7, ARM Cortex‑A).
Key differences between polling and interrupt-driven I/O? When prefer each?
Polling repeatedly checks a flag—simple but wasteful. Interrupts signal events—more efficient, lower latency. Use polling for tight-loop or simple tasks; use interrupts when events are sparse or real-time response is needed.
Explain the role of a watchdog timer in embedded systems.
A watchdog is a hardware timer that resets the system if not periodically kicked by firmware. It recovers from hangs or deadlocks, ensuring reliability in unattended devices.
What are memory-mapped I/O and port-mapped I/O? Describe differences.
MMIO shares the CPU’s address space for peripherals accessed like RAM. Port-mapped I/O uses a separate I/O space with special instructions (e.g. x86 IN/OUT). MMIO is common in MCUs.
Purpose of using volatile variables in embedded C? Example.
volatile prevents compiler optimizations on variables changed outside program flow (e.g. hardware registers or ISR flags). Example: volatile uint8_t dataReady; set in ADC ISR.
What is debouncing and why is it necessary?
Mechanical switches bounce, generating multiple transitions. Debouncing filters noise via hardware RC or software delay/state machine so one press equals one event.
Difference between hard real-time and soft real-time systems? Examples.
Hard RTOS must meet deadlines 100% (e.g. airbag controller). Soft RTOS allows occasional misses with performance penalty (e.g. multimedia). Hard uses tighter scheduling guarantees.
What is DMA and how does it improve performance? Use case.
DMA transfers data between memory and peripherals without CPU, freeing CPU for tasks and reducing latency. E.g. streaming ADC samples into RAM while CPU processes previous buffer.
Difference between cooperative and preemptive multitasking? Advantages/disadvantages.
Cooperative: tasks yield control voluntarily—simple, low overhead, but one task can block others. Preemptive: scheduler interrupts tasks—better responsiveness, but adds context-switch overhead.
Common causes of stack overflow and how to prevent or detect it?
Deep recursion, large local arrays, unbounded interrupts. Prevent via static analysis, limit recursion/buffer sizes, measure via stack canaries or fill with pattern to check watermark.
How does an interrupt vector table work?
A fixed-address array of function pointers. On interrupt, CPU indexes the table, fetches ISR address, and jumps. It centralizes and maps interrupts to handlers.
Difference between static and dynamic memory allocation? Trade-offs.
Static is deterministic with no fragmentation—preferred in MCUs. Dynamic (malloc/free) is flexible but risky (fragmentation, unpredictable latency)—use pools or avoid in tight systems.
What are race conditions and how to prevent them?
Race conditions occur when concurrent contexts access shared data unsafely. Prevent with mutexes, disabling interrupts, atomic ops. E.g. ISR and main both updating a multi-byte counter.
What is memory alignment and why important?
Alignment places data on natural boundaries (e.g. 4‑byte on 4‑byte boundary). Misaligned access can cause slow or fault on some architectures—always align data structures.
Explain priority inversion and how to handle it.
Low‑priority holds a mutex, medium preempts, high waits—low never runs. Mitigate via priority inheritance or ceiling protocols to boost low’s priority temporarily.
Difference between a bootloader and firmware? Roles during startup.
Bootloader initializes hardware, verifies/updates and loads firmware. Firmware is the main application. Bootloader runs first, then jumps to firmware entry.
Difference between bare‑metal programming and using an RTOS?
Bare‑metal has no OS—low overhead, full control, manual scheduling. RTOS provides tasks, IPC, timers—faster development but adds footprint and switching overhead.
Role of an RTOS scheduler? Round‑robin vs priority‑based.
Scheduler picks the next ready task. Round‑robin cycles same‑priority tasks equally. Priority‑based runs highest‑priority ready task, preempting lower ones.
Ensure data consistency between ISR and main program?
Use volatile, disable interrupts during shared access, atomic operations, or lock-free buffers. Example: ring buffer for UART RX.
What is a memory leak and why is it problematic?
Memory allocated but never freed accumulates until OOM—critical in small RAM. Detect via heap tracing, guard blocks. Prevent with pools or avoid dynamic alloc.
Key considerations for low‑power design? Techniques.
Minimize active time, sleep modes, clock gating, voltage/frequency scaling, batch I/O, DMA usage, wake on interrupt, optimize code paths.
Difference between ISR latency and execution time? Importance.
Latency is time to start ISR after event; execution time is duration ISR runs. Latency affects responsiveness; execution time impacts scheduling and interrupt blocking.
Typical stages in embedded software lifecycle?
Requirements → design → implementation → testing → integration → deployment → maintenance. Ensures reliability and traceability.
How handle clock drift? Clock synchronization techniques.
Crystal calibration, periodic NTP/PTP, external RTC modules, GPS reference, temperature‑compensated oscillators.
