Exam 1 Flashcards
(20 cards)
In a combinational logic circuit output values depend on
Only present input values, less a non-zero, combinational logic path propagation delay
In a finite state machine in which the output values depend exclusively on the present state value, the output values may change
Only during a clock event
Which of the following coding styles is NOT a “one-to-one” match with a schematic drawing?
Behavioral
Statements inside a procedural block (always in Verilog or process in VHDL) are executed:
Sequentially
Which language does NOT have built-in primitives (gates)?
VHDL
A circuit described in VHDL has
An entity and one or more architectures
In VHDL, if X is of type std_logic_vector(7 to 0), and X <= “10100101”, then the value of x(6) is
‘0’
In Verilog, if X{7:0] = 8’b10100101, then the value of X[3] is
‘0’
Which type of simulation DOES NOT use accurate gate and wire propagation delay?
Functional
Is a testbench being/or not being synthesized?
Testbench is not being synthesized
High level programming languages such as C describe
Only sequential events
If the value of a parameter in Verilog is not specified at the time of instantiation, then the tool chooses to use
The default value
A process in VHDL or always block in verilog is entered and executed when
one or more signals in the sensitivity list change state and when ALL signals in the sensitivity list change state
Port mapping in VHDL can be done using
positional association and named association
During exhaustive verification or testing, what combinations are exercised?
All possible input combinations are exercised
A testbench module in verilog has:
- only input ports
- only output ports
- input and output ports
- none of the above
None of the above
Calculate the following sum and determine if overflow occurs.
10001101
+ 01001101
——————
These operands are 8-bit 2’s C-signed integers. The values of C and V are
MSB is neg = 1 and pos = 0
If the sum of two positive numbers yields a negative result, the sum has overflowed.
If the sum of two negative numbers yields a positive result, the sum has overflowed.
Otherwise, the sum has not overflowed.
Overflow= V=0 Cout = resulting MSB=0
Which number is represented by the following Verilog description {4’b0101, 4’hA)?
01011010
Verilog HDL allows integer numbers to be specified as
Sized or unsized numbers bits
In a radix: binary, octal, decimal,hexadecimal
Radix and hex digits (a,b,c,d,e,f) are case insensitive
Syntax: ‘;
If 1010 is 4-bit 2’s C value, then the same value in 8-bit 2’s C representation is
1111_1010
Overflow can be detected by applying one of the following rules
Sign of the results is different than that of both operands and when the carry in and out of the most significant bit position are different
