Exam 2 Flashcards
(133 cards)
1
Q
ISA
A
Specifies the software interface to the CPU
(Instructional Set Architecture)
2
Q
Microarchitecture
A
- hardware design of a physical CPU
- an implementation of an ISA
3
Q
Control
A
Tells everything else what to do and when
- decode the instruction and set all the control signals to make that instruction happen
- automatically sets the control signals to the right values to make each instruction happen
4
Q
Registers
A
- Hold the values being computed
- temporary stopping point for your program’s data
5
Q
ALU
A
Computes new values from old values
Arithmetic and Logic Unit
6
Q
Values move between what
A
Registers and ALU
7
Q
Architectural Registers
A
- registers that the ISA specifies
- GPR < Architectural < Microarchitectural
8
Q
GPR
A
registers you can use for any purpose in programs
- General Purpose Registers
9
Q
Microarchitectural registers
A
- exist outside the ISA and are part of the implementation of the CPU
- used for temp storage, implement multistep operations, control specific features, etc.
- Often inaccessible from software
10
Q
Register File
A
- Holds General-purpose registers
- like an array of registers or small word addressed memory
11
Q
PC register
A
- part of the control
- says what step to do next
12
Q
PC
A
memory address (send it to memory)
- memory sends back data (instruction) and the control decodes the instructions and tells things what to do
Program Counter
13
Q
CPU’s Job
A
to read and execute instructions
(Fetch, Decode, Execute (Once per instruction))
14
Q
Fetch
A
gets the next instruction to execute from memory by using PC
- Instruction memory
15
Q
Decode
A
Control reads the instruction
- look at the fetched instruction and set control signals
Control/Register File
16
Q
Executes
A
The control does the instruction by telling other parts what to do
- wait for data to flow through the ALU
ALU
17
Q
how many times is memory accessed for a load or store?
A
-1st access: to fetch instruction
-2nd access: to actually load the value
18
Q
Schematic
A
Graphical way to represent systems (flowcharts)
19
Q
HDL
A
Hardware Description Languages (text)
20
Q
EDA
A
Electronic design automation (schematics)
21
Q
Schematics and texts are…
A
equal in power
22
Q
Circuit schematics show…
A
how data flows from one component to another
23
Q
components can
A
produce or consume values (or both)
24
Q
Is there order in circuit schematics?
A
NO
everything in the circuit happens simultaneously
25
Boolean Function
takes one or more Boolean (t/f) inputs and produces a Boolean output
26
truth table
summarizes a Boolean function by listing the output for every possible combination of inputs
27
gate
implements one of the basic Boolean logic functions
28
What can all computation be built from
All computation can be built from just the basic Boolean logic operations (AND, OR, and NOT)
29
Add two three-bit numbers
- need three one bit adders
- chain the carries from each place to the next higher place
30
Propagation Delay
every gate and wire has it
- the amount of time needed for a signal to "propagate" through it
31
ripple carry
linear in the number of bits
- if you double number of bits, double the amount of time needed
32
overflow
Get a number too big to be represented and it gets wrapped around
33
If you add two n-digit numbers in any base...
the result will have at most n + 1 digits
34
3 options to deal with overflow
1. store
2. ignore
3. fall on the floor (crash)
35
Ignore option
- worst and most common way to respond to overflow
36
Crash option
- better than ignoring
- generates CPU Exception (can be detected and handled)
37
Arbitrary Precision Arithmetic
two 8-bit adds, starting with LSB
- the carry bit from the first add is carried into the second add
- can keep chaining them together
38
overflow in unsigned addition
in unsigned addition, if the MSB has a carry out of 1, an overflow happened
39
overflow in signed addition
in signed addition, overflow occurs if we add two numbers of the same sign and get the opposite sign
40
signed subtraction
same as signed addition, apply the rule after doing the negation
41
overflow for unsigned subtraction
overflow occurs when the MSB's carry out is 0 not 1
42
overflow for signed subtraction
same as addition, but check after negating second input
43
two paths can be done...
at the same time
44
when making a decision in hardware you...
do all possible things, then pick only the thing you need, and ignore the rest
45
Multiplexer
(mux)
- outputs one of its inputs based on t=a select input
46
Demultiplexer
(Demux)
- opposite of multiplexer
(with very few exceptions, you won't need these)
47
negate means
change the sign to the opposite
48
shifting left by n is the same as...
multiplying by 2^n
49
shifting right by n is the same as...
dividing by 2^n
50
Arithmetic Right Shift
used for signed numbers
- "smears" the sign bit into the top bits
(pushes 1s in the left place while scooting right)
51
And
intersection
set of things that are in both sets
52
Or
Union
the set of things that are in either set
53
XOR
Symmetric set difference
set of items in one set but not both
54
Mask
specifically constructed value that has 1s in the bits it wants to keep and 0s in the bits that we want to discard
(& 000001111, 1s being the bits we want to keep) (same is doing 1st number mod 16)
55
To isolate the lowest n bits,
And with 2^n-1 or bits & ((1 < < n) - 1
56
no finite number of fractional places can
represent infinite fractions, because writing infinite fractional places would require infinite storage
57
how are floats represented
as a fixed-length binary number with fractional places
58
every operation on floats round
the result off to the nearest representable float
- (a + b) + c may not be equal to a + (b + c)
59
floats don't use what?
2's complement
(they use sign magnitude)
60
Combinational Logic
you give it some combo of inputs and you get an output
61
one kind of memory
a circuit that remembers information and memory is the basis of sequential circuits due to propagation delay
62
sequential circuits
can perform sequences of operations
63
clock signal
says when we move to the next step
64
clock edges
when it changes between 1 and 0
rising and falling edges
65
clock cycle
time from one rising edge to another rising edge
66
write enable
like a door on the input of the register
67
when the write enable is 0
it ignores the clock and the value never changes
chooses if we change a register's value on each cycle
68
state
all the things remembered by the system
69
blinky states
on or off
70
state transition table
sequential version of a truth table
encodes the same information as a state transition diagram
71
FSM
Finite State Machine
way of thinking about a sequential process where there is state (memory), the state changes based on the current state transition logic and (optionally) inputs, there are outputs based on the states
72
is multiplication slower than addition
yes
73
when you multiply two n-digit/bit numbers
the product will be at most 2n digits/bits
74
division
factoring polynomials
fundamentally slower
75
how many addresses can you access in memory
You can only access one address in memory per clock cycle
76
if you have one kind of resource and you want two users to use it, you have two options
- make two instead of one so they can use them simultaneously
- make the users take turns using one, over time
77
Harvard Architecture
2 memories
- PC -> Instruction on memory -> instructions
- stores -> data memory -> loads
- easier for hardware designers
78
Von Neumann
One memory (takes turns)
- PC, Stores -> Memory -> instructions, loads
- uses multiple clock cycles
- fetch instruction on first cycle
- perform variable load on second cycle (most common but more complex)
- easier for programmers
79
Assemblers job
turns assembly language code (written by humans) into machine code (for the CPU to read) based on ISAW
80
What makes instructions smaller
encoding instructions as bitfields
81
jump
make execution go to one specific place
- absolute
- jumps (j, jal, jr) put a value (the jump target) into the PC
82
branches
make execution go to one of two places
- relative
83
absolute
sets the PC to a new value
84
relative
it adds an offset to the current PC
85
offset
destination - here (calc by assembler not CPU)
86
FDXMW
Fetch, Decode, Execute, Memory Access, Write-back
87
Memory Access
If its a load or store, do that
Data memory
88
Write-back
If theres a destination register, write the result to it
Register File
89
3 phases of decoding
1. split the encoded bitfield into its constituent values
2. from the opcode, determine which instruction we're looking at
3. map that instruction to a unique combination of control signals
happens in control unit
90
overall shape of control
- the only input is current instruction, which gets split up
- the opcode gets decoded to produce the instruction signals
- the instruction signals are used to come up with the control signals
- the outputs are some instruction fields and the control signals
91
small numbers have
negative exponents
92
large numbers have
positive exponents
93
when you move the decimal to the left
you add to the exponent
94
when you move the decimal to the right
you take away from the exponent
95
(T)era
10^12
96
(G)iga
10^9
97
(M)ega
10^6
98
(K)ilo
10^3
99
(m)illi
10^-3
100
micro (weird u)
10^-6
101
(n)ano
10^-9
102
(p)ico
10^-12
103
Latency
how long a task takes to complete
- seconds per task
104
Throughput
how many tasks you can complete in a span of time
- tasks per second
105
improving latency
reducing amount of time that one task takes
106
improving throughput
increasing the amount of work being done at once
107
what is the best latency
shortest latency
(time/task)
108
what is the best throughput
the one with the highest number of completed tasks
(tasks/time)
109
making latency lower
can make throughput higher
110
critical path
path through a circuit that requires the longest series of sequential operations
111
fastest we can clock a sequential circuit
is the reciprocal of the critical path's propagation delay
112
problem with single cycle architecture
- it ties the performance of the CPU to the performance of the RAM
- clock cannot tick any faster than the instruction with the longest critical path
- can't run the clock any faster than memory latency
113
what is the fastest a single cycle machine can run
66-83 MHz (66 to 83 million)
1 CPI
114
pipeline registers
hold onto data for the next phase in multi cycle
115
CPI
(Cycles Per Instruction)
- latency
- how many cycles it takes to complete one instruction
- lower is better (slower instructions take more cycles)
- Best is 1
116
Total time
n * CPI * t seconds
117
Microprogramming
Control is a FSM whose transition table is in a special memory
118
microcode
(ucode)
small "programs" that encode the sequence of steps for each instruction
119
sequencer
decides what steps to do next (control flow through uProgram)
120
uInstruction
set of controls and FSM control flow information
121
uCode ROM
(read only memory)
indexed by the uPC
122
hardware control is faster
because it is smaller and simpler
123
the longer the sequence of instructions gets
the closer the CPI
124
the more stages instruction have
the higher the throughput gets
125
cache
temporary holding area for recently used data
(memory references cache)
126
temporal
these variables are used over and over, very quickly. It makes sense to keep them somewhere fast to access
127
spatial
the items in this array are all next to each other in memory. the cache will pull in several items at a time
128
scalar CPU
finish at most 1 instruction per cycle
129
superscalar CPU
finishes more than one instruction per cycle
130
pipelining
partially overlapping instruction execution to improve throughput and complete instructions faster
131
Caching
keeping copies of recently used data in a smaller but faster memory so it can be accessed more quickly in the near future
132
Out-of-Order
CPUs analyze several (a dozen or more) instructions in advance, then dynamically reorder them so they can be executed more quickly then they would as written
133
