Exam Prep Deck

Question 1

What factors limit the increased throughput that can be obtained using pipelining in complex designs such as a microprocessor data path?

Answer 1

Diminishing returns with each pipeline stage added due to the setup and propagation times of the flip- flop. Also, complex circuits such as the microprocessor data path have dependencies between the pipeline stages (data and control hazards) which require additional logic and delays to overcome and hence do not achieve the expected speed up.

Question 2

Question iii)

Answer 2

The critical path length is now (3 x RAM delay) + (3 x mux delay) = (3 x 500ps) + (3 x 50ps) = 1650 ps

The minimum clock period = critical path + setup + clock-to-Q = 1650ps + 50ps + 70ps = 1770 ps

Maximum clock frequency = 1/2870ps = 565MHz

Question 3

Briefly describe the verification process for digital designs

Answer 3

The desired behaviour of the digital circuit is captured in a HDL (hardware description language_)_ such as SystemVerilog. A set of test inputs or “test vectors” are generated which cover all the expected operating conditions of the circuit. Another HDL code, the test bench, is used to apply the test vectors to the circuit in simulation and the outputs are captured. A software model of the circuit behaviour is also created. The HDL simulation and software model outputs are compared to detect logical errors in the HDL code before synthesis starts. This process reduces the probability that defects will be present in the final product.

Question 4

Architecture

Answer 4

Price lowest to highest: ASIC -> Microprocessor -> FPGA

Question 5

Define Setup error

Answer 5

The input to a sequential element such as a flip-flop must be stable a certain time before the clock edge, known as the setup time. A setup error occurs when this condition is not met.

Question 6

Work out DCO tune as an integer?

Answer 6

1. Pick a range(DCORSEL).
2. Select the desired frequency within that range (FDCOnom).

Question 7

Explain the following terms in the context of the digital design process.

(i) Constraints
(ii) Recurring costs

(iii) Non-recurring costs

Answer 7

Constraints: requirements which have been identified for the design, for example, minimum clock frequency, maximum delays, maximum area etc.

Recurring costs: costs which have to be paid each time a chip is manufactured, including fabrication, testing and packaging

Non-recurring costs: costs which must be paid before a chip can be manufactured, including design and tooling costs

Question 8

Specify the contents of the RAM blocks in a CLB to create a 2:1 multiplexer

Answer 8

Assign I0 and I1 on the 16x1bit RAM to be the 2 bits of D. Assign I2 on the 16x1bit RAM to be S, I3 is a “don’t care”.

A single CLB can represent the mux with the following RAM entry:

(to get the address values just combine all the row elements from left to right.

I0 is 4 zeros followed by 4 1s

I1 is alternating sets of pairs

I2 is simply alternating going down.

I3 is just x’s for all the bits.

Question 9

(i) Explain how the current state variable is updated using the state table implementation approach in c code.

Answer 9

The new state is simply updated using array indexing where the row index is the event value and the column index is the current state. The updated state is given by the value at this memory location.

state = statetable[event][state];

Question 10

4:1 multiplexor a behavioural style with case statements

Answer 10

Question 11

Define what is meant by static timing analysis.

Answer 11

In static timing analysis, the delay of every combinational path between sequential elements is calculated. These are used to assess whether each sequential element meets it’s setup and hold conditions under a set of timing constraints such as clock frequency and jitter.

Question 12

Write C code to implement the action handler for the actiontable, assuming there is a current state variable currentstate and an event variable event. You can assume the action functions: fcn0() … fcn3() are already defined.

Answer 12

Question 13

Do q b)

Answer 13

Question 14

Sketch the block diagram of the circuit in terms of the adder and flip-flop cells.

ii)

Answer 14

Question 15

What is a precision ADC?

Answer 15

module that can achieve over 16bit precision using software oversampling, up to 1 Mbps sampling rate with differential and single ended inputs.

Question 16

Describe the concept of corner analysis and how it would be applied to variations of Vdd across a digital integrated circuit.

Answer 16

Corner analysis ensures that a high proportion of the chips fabricated will work across all the process and environmental variations. It involves carrying out static timing analysis at the extreme operating conditions or “corners”.

In the case of power supply variation, gates with a low value of Vdd will run slow and hence be more susceptible to setup errors. Gates with high Vdd will run fast and be more susceptible to hold errors. A corner analysis including Vdd variation could include static timing analysis with (1) low Vdd, slow transistors due to process variation and high temperature to ensure that setup errors do not occur and (2) high Vdd, fast transistors and low temperature to ensure that hold errors do not occur.

Question 17

When using an input pin on a microcontroller as an analogue input what will the input impedance be?

Answer 17

The pin will be in the high impedance state

Question 18

Explain how Pulse Width Modulation (PWM) is used to control the speed of the motors and describe how it is implemented in microcontroller hardware.

What are the key words/terms you need to remember

Answer 18

PWM is a method of producing an analogue voltage level from a digital output. A PWM signal consists of a periodic pulse train whose frequency is much higher than the frequency of the device or system that is been driven. The signal amplitude is then adjusted by varying the pulse duration or duty cycle. The output waveform is then lowpass filtered, either by a specific low pass filter or simply by the response time of the system that is been stimulated, to produce the analogue waveform. In a microcontroller this is implemented using a timer/counter and two counter compare registers. The timer/counter is clocked at a certain rate 𝑓_𝑐𝑙𝑘 using a divided version of the system clock. One counter compare register is used to set the maximum count and hence the period of the PWM signal i.e. 𝑇 = 𝑀𝑎𝑥𝐶𝑜𝑢𝑛𝑡 / 𝑓𝑐𝑙𝑘 . The other compare register is used to set the duty cycle and hence the output amplitude.

Key words/terms to remember: analogue voltage level, periodic pulse train, duty cycle, low pass filter, timer/counter, counter compare registers, maximum count, output amplitude

Question 19

Explain what is meant by Dennard scaling in the semiconductor industry.

Answer 19

Question 20

Define pipelining

Answer 20

Partitioning a circuit or algorithm into multiple stages, separated with sequential elements, in order to increase the clock speed and throughput.

Pipelining involves splitting up the functions performed by the combinational logic into separate functions and inserting sequencing flip-flops or registers into the path. Because the delay of the combinational logic in each pipeline stage has been reduced, the clock frequency can be increased or supply voltage can be reduced to save power.

Question 21

(iii) What is the maximum throughput of the circuit, i.e. the number of sum outputs generated per second?

Answer 21

The minimum clock period is the sum of 3 adder cell propagation delays and the flip-flop setup and clock-to-Q propagation delays.

Minimum period = (3*300ps)+50ps+65ps = 1015ps.

The maximum clock speed or throughput is, therefore, 1/1315ps = 985MHz

Note that they cheekily put maximum propagation delay of adder cells outside of the table.

Question 22

16 bit vs 8 bit

Answer 22

The 16-bit processor will be two times faster.

Question 23

Define: Non-recurring costs

Answer 23

Non-recurring costs are any costs which must be paid before any products can be fabricated including d_esign engineering costs_, prototyping, product–specific equipment required for design, product-specific manufacturing equipment such as photomasks and packaging tools

Question 24

Define Standard Cell Library

Answer 24

A set of predefined characterized layouts of basic logic functions such as AND, OR, invert, flip-flop, latch, multiplex etc. The cells have fixed height and variable width to allow a circuit layout on a regular grid, speeding up development times.

Question 25

Write C code to initialise pins 0-3 on PORTC as inputs with pull-ups enabled and 4-7 as outputs set to logic high. Then store the state of pin 3 as a char. You may assume that PORTC, DDRC and PINC are defined

Answer 25

DDRC=0xF0; PORTC=0xFF; char state=(1\<\<3)&PINC;

Question 26

Show how to build a 4:1 multiplexer with the minimum number of CLBs.

Answer 26

A 4:1 mux can be built from _3 x 2:1 muxs_ arranged in a **tree** structure. The minimum number of CLBs is therefore **3**.

Question 27

Explain the advantage that the state table implementation provides in comparison to a nested if statement implementation.

Answer 27

In the state table approach the functionality of the machine is encoded in the state transition and action tables and an identical piece of code is used to implement the state machine regardless of the complexity of the machine. This means that the operation of the machine can easily be changed by simply updating the state table without needing to change the code. If the nested if approach is used then the code must be changed which is harder to keep track of and debug.

Question 28

ADC Interfacing system

Answer 28

Transducer Interface Design (TID) circuit:Scale and shift transducer output signal range. Scale: Map the span. Bias: Shift scale to align with ADC input. V2max = (V1max\*K)+B. V2min = (V1min\*K)+B.

Question 29

Total Power Consumption of circuit with sequential elements

Answer 29

Question 30

A microcontroller with a clock frequency of 16MHz is used to create an analogue output using PWM suitable for the reproduction of voice signals recorded with 7 bit resolution. (i) How many bits does the counter require to provide the required resolution and what should the maximum count value be set to?

Answer 30

The counter would only require 7 bits to provide the required resolution, however the _dedicated counters_ in a typical microcontroller are _either 8 or 16 bit_, using a 8 bit counter with the maximum count set to 127 would provide the correct resolution. how do you find the maximum count from 7bit resolution? 2⁷ - 1. So 2ⁿ - 1 is the formula.

Question 31

Explain what is meant by the following terms, relating to the timing of synchronous sequential circuits: 2018 - q2 - a

Answer 31

(i) For the circuit to sample its input correctly, the input must have _stabilized_ at least _setup time_, tsetup, **_before_** the _active edge_ of the clock. (so the input was be stable for set amount of time before active edge) (ii) For the circuit to sample its input correctly, the input must remain stable for at least the _hold time_, thold, **_after_** the _active edge_ of the clock. (so input must remain stable for hold time after the active edge) (iii) When the clock’s active edge occurs, the _output may start to change after the clock to-Q **contamination** delay_, tccq. (iv) When the clock’s active edge occurs, the _output must definitely settle to the final value within the clock-to-Q **propagation** delay_, tpcq.

Question 32

Table you need to remember to convert binary to hexadecimal

Answer 32

note that the change from number to letter is from 9 to 10

Question 33

Explain the meaning of line 3 of the code in Figure 1.1

Answer 33

Defines two _bit vectors_ I and Q each with _8 bits_. The **logic** type is used in SystemVerilog to _model signals_ in digital circuits – it has 4 possible values 0, 1, X (unknown) and Z (high impedance).

Question 34

The circuit above is to be used in a low power application. (i) Explain how pipelining can be used to reduce power consumption of the circuit without reducing the clock frequency.

Answer 34

Placing the two combinational functions in different pipeline stages means that the _delay in each combinational function can be increased by reducing the supply voltage_. In this case, it is the 2nd combinational stage which will limit the performance. The current clock frequency can be maintained if the delay of the 2nd combinational stage is increased to _1.5ns_. Key thing to remember is that delay in each combinational element of the pipelined circuit can be increased by reducing the supply voltage, leading to the same clock frequency but lower power consumption.

Question 35

bit width of ADC module

Answer 35

32-bit

Question 36

Pointers

Answer 36

A pointer is a variable whose value is the address of another variable, i.e., direct address of the memory location. Pointers always begin with an asterisk \* Pointers should be _initialised as NULL_ _when the intended address is not known_. Uninitialised pointers can be pointing to a memory address used by the system unintentionally. Allows NULL checks before accessing a pointer

Question 37

Do questoin b)

Answer 37

Question 38

What do you need to remember about switch models and inividual CMOS inverters?

Answer 38

When you draw an individual CMOS you combine the C_n and C_p for the pMos part, i.e where V1 goes into.

Question 39

i) Draw the equivalent circuit for calculation of the rise/fall times.

Answer 39

Question 40

If the code in Figure 1.1 was simulated, sketch a waveform showing the signals clock, reset, enable, direction and I from the start of simulation up to 250 ns. Express the values of I in hexadecimal. Ensure that the times of signal transitions are clear.

Answer 40

Question 41

CMOS Switching energy: 2018 - 3 - c)

Answer 41

Question 42

Briefly discuss increasing the throughput of digital circuits, with architectural and technology considerations.

Answer 42

_Technology_: use a more advanced CMOS process with a **shorter gate length**, Use _full custom design_ techniques or a _standard cell library_ which is better optimized for the application _Architectural_: Besides pipelining, parallel processing is the main technique, involving duplicating logic without increasing the clock speed. This is limited by the area available for the circuit.

Question 43

If you're looking for a fully stable output out of a logic gate, what timing parameter are you looking for?

Answer 43

t_pd propagation delay

Question 44

Calculate the reduction in power consumption that can be achieved by pipelining without changing the clock frequency, activity factor or threshold voltage and assuming that a single power supply is used for the whole circuit.

Answer 44

Note that the new t_pd is 1.5ns for the pipelined circuit with the same frequency as the original circuit.

Question 45

Multiplexors an pipelining

Answer 45

The combinational logic of the 32:1 mux must be split into 2, ideally with roughly equal critical paths. As the critical path of the 32:1 has 5 x 2:1 stages, it cannot be split equally so the optimum is to have 8:1 muxs in 1 pipeline stage and 4:1 in the other (the 8:1 and 4:1s are constructed from 2:1 building blocks as previously described) The clock frequency is increased because the critical path is now through the 8:1 mux which consists of only 3 CLBs.

Question 46

What is the nominal threshold voltage of a MOSFET, Vt?

Answer 46

can be varied by changing the channel length or channel doping concentrations, but its nominal value is typically half of the supply voltage, V_DD/2.

Question 47

Microcontroller Question

Answer 47

Question 48

What's an important thing to remember when creating case statements in C compared to the HDL system verilog?

Answer 48

You define a case with switch() Then the individual cases are set inside. e.g. switch(fun){ case 0:{ } case 1:{ } }

Question 49

Maximum clock frequency of multiplexor

Answer 49

Following from the answer to (b), the number of stages in an N:1 multiplexer is **log2(N)**. Since the N=32, the critical path is through log2(32) = 5 CLBs. The critical path length is (5 x RAM delay) + (5 x mux delay) = (5 x 500ps) + (5 x 50ps) = 2750 ps The minimum clock period = critical path + _setup_ + _clock-to-Q_ = 2750ps + 50ps + 70ps = 2870 ps Maximum clock frequency = 1/2870ps = 348MHz In this case the ram and multiplexor delays are multiplied by 5 and the one time setup time clock-to-Q delay are added.

Question 50

If you applied pipelining to this circuit, what do you need to remember?

Answer 50

the slowest combinational logic block will dictate the new minimum clock period and hence maximum freq. In any previous clock period can have 0.5ns removed.

Question 51

4 b i) Explain how an FPGA can be used to implement arbitrary digital systems including both combinational and sequential logic elements.

Answer 51

The FPGA needs to be programmed to implement the desired logic by _changing the contents of the RAM blocks_ using the _reconfiguration bus_. Any 4-input, single output combinational function can be implemented by setting the contents of the _16 x 1bit RAM_. The 4 CLB (cofigurable logic block) inputs _represent the address lines_ of the RAM. For example, a 4-input AND gate can be created by setting all entries of the RAM to 0 except for entry 15 ({I1,I2,I3,I4} = 1111) which should be 1. By configuring the _1-bit RAM_ which controls the _2-port multiplexer_, the output of the combinational block can be connected directly to the CLB output or to the flip-flop for sequential logic. By creating an array of CLBs with reconfigurable interconnect, complex digital systems can be created. Key things to remember here: any 4 input single output combinational function can be created in 16x1bit RAM. The 1 bit RAM controls the 2 port multiplexer meaning that the output of the combinational block can be connected directly to the CLB output or to the flip-flop for sequential logic

Question 52

What does adding a 3 stage pipeline do to the maximum clock frequency of this circuit?

Answer 52

a register would be placed after each adder cell maximum clock frequency would increase 3 fold in this case.

Question 53

Describe the difference between a synchronous reset and an asynchronous reset.

Answer 53

A **synchronous** reset only takes effect _in response to a clock event_. An **asynchronous** reset takes effect _immediately independent to the clock_.

Question 54

Dennard Scaling

Answer 54

Question 55

Nyquist frequency

Answer 55

minimum sampling rate you need to represent an analogue by its digital equivalent accurately. f_s \>= 2\*f_H f_H highest frequency available.

Question 56

What is an Action and what is an Activity?

Answer 56

Action (f-transition): an executable function associated to a _transition_. _**Not** interruptible_. Activity (f-state): an executable function associated to a _state_. **_Is_** _Interruptible by an event_

Question 57

When using the 10 bit Analogue to Digital converter (ADC) on an 8 bit microcontroller to sample a human voice: What frequency should the ADC sample clock be at least? What type of C variable is required to hold the converted output from the ADC?

Answer 57

The highest frequency component in human voice is typically 20 kHz, thus sampling at 40 kHz would meet the Nyquist criterion. 16 bit word, e.g. int

Question 58

Describe the operation of the shift register, in particular, specifying how the output, R, changes in response to the inputs.

Answer 58

If the reset is high (independent of the clock), R is held at 0. If select S is high, on each positive clock edge, R takes the value of the input I. If select is low, on each positive clock edge, R is shifted to the left by 1 bit with a zero inserted into the least significant (right-most) bit. Remember the curly brackets with two or more terms inside means concatenation. In this case everything up to N-2 is selected and a zero is added to the end. Thus R is getting shifted to the left by 1 bit at a time.

Question 59

Define: Application specific integrated circuits

Answer 59

An ASIC is any digital circuit designed and fabricated for a dedicated purpose, i.e. not using programmable hardware or general purpose software-programmable processors.

Question 60

ADC subsystems

Answer 60

Question 61

Window comparator

Answer 61

basically the inverting and the non-inverting comparators from the precision ADC combined into a single comparator stage.

Question 62

Action table

Answer 62

The action table contains the function codes for each possible state and input condition. The correct function is determined by doing a lookup using the event value for the row and the current state for the column index.

Question 63

An inverter in a standard cell library implemented in a 45 nm CMOS process has the following measured propagation delays at the typical corner, shown in Table 3.1 Explain why the inverter cell has finite propagation delay at zero load capacitance.

Answer 63

Chains of logic operate by each logic gate charging/discharging the gate capacitance of the load logic gates. The gate capacitance of the MOSFET is essential to the device operation, but the source and drain also have a capacitance which is **parasitic**. The _propagation delays at zero load capacitance_ are due to the _charging/discharging of this parasitic capacitance_.

Question 64

Reducing power consumption of digital circuits

Answer 64

Question 65

For each of the following SystemVerilog code fragments, state whether it represents a realisable digital circuit and explain why.

Answer 65

Example (i) is not a real circuit. In simulation, always\_comb blocks are executed when any of the right hand side parameters change, so this code will advance count by 4 each time it executes but continue executing for ever at the same simulation time. On the other hand, (ii) is a correct counter as it uses sequential logic which is only executed on the positive clock edge. Fragment (iii) is correct and represents 4 AND gates operating in parallel. New values of c will be generated whenever any value of the arrays b or a change.

Question 66

Definition of Propagation delay of combinational logic

Answer 66

Propagation delay is the time taken for the output of combinational logic to fully stabilise after a change in the inputs.

Question 67

Define: Photomasks

Answer 67

Features are created on the silicon wafer by covering the wafer with a _photoresistive material_ and exposing the wafer to _ultraviolet (UV)_ light through a _photomask_ which contains the desired pattern of the circuit. The photoresist which has been exposed to UV hardens and remains when a chemical process is used to _wash the unexposed photoresist away_. Ion implantation or laying down metal, polysilicon or oxide layers on selected areas of the wafer can then take place. Each step in the process requires a photomask.

Question 68

Define Clock-to-Q propagation

Answer 68

Clock to Q propagation delay is the time between the clock edge and the output of the flip- flop or register stabilising.

Question 69

Microcontrollers: When using the pins for digital input the preferred mode is to enable pull-ups.

Answer 69

This ensures that when the pin is _not connected to anything_, e.g. an open switch, that the state of the pin is _not left simply floating_ and _therefore indeterminate_ which is why it is _pulled up to Vcc_.

Question 70

Explain why are the I/O pins on a microcontroller are called tristate inputs?

Answer 70

The pins can be in one of three states either be _pulled up to +Vcc_ or _set to ground_ or in a _high impedance floating state._

Question 71

If you know the propagation delay, time setup and clock-to-Q time, what can you calculate?

Answer 71

clock period from which you can get the max clock freq.

Question 72

Dennard Scaling limitations

Answer 72

Both oxide thickness and threshold voltage have _reached scaling limits_. _Scaling oxide thickness_ further causes **leakage current** to increase due to **tunneling**. _Scaling threshold voltage_ causes **sub-threshold currents** to increase when the MOSFET is off. In both cases, further scaling would cause _leakage power to dominate_ overall power consumption which is already a problem for high performance digital systems. scaling oxide thicknes -\> leakage current b/c of tunneling scaling threshold voltage -\> causes sub-threshold currents thus further scaling causes leakage power to dominate

Question 73

Explain what an interrupt is and give an example of how you would use one in this application.

Answer 73

Interrupts provide a way of allowing the microcontroller to _respond to events without the CPU having to continuously poll_ for a particular event. For example, in this application, an edge detection interrupt could be used to detect the change of state of a digital input corresponding to a switch press. When the CPU receives the interrupt it _first stops_ what it is currently doing and _then carries out the appropriate action_ for the interrupt. Once the CPU has serviced the interrupt it _resumes the previous operation_.

Question 74

What does #() when instantiating a module?

Answer 74

some modules need a parameter passed through, and this is the syntax to do it. placed inbetween the module name and your module label.

Question 75

Total power consumption of a circuit with sequential elements?

Answer 75

Question 76

Explain how the operation of a for loop differs between SystemVerilog and a software language such as C++ or Java?

Answer 76

In a software language, a for loop defines actions which will be carried out in series. In synthesisable SystemVerilog code, for example within **always\_comb** or **always\_ff** blocks, a for loop represents circuits which will _operate in parallel_.

Question 77

timing constraints: hold time 2018 - q2 - b

Answer 77

Question 78

Explain the meaning of line 6 of the code in Figure 1.1.

Answer 78

Line 6 “instantiates” or defines a submodule within the tb\_shiftreg module. In this case the module name is **shiftreg** and it is given the label _uut_. The shiftreg module has 1 parameter which in this instantiation is given the value 4. The Q, I, direction enable, clk, reset signals are connected to the ports of shiftreg in the order that they are defined in the code. So when you don't know the order of the values of a module instantiation in a module you just assume the order in which they are defined in the parent module?... i guess just remember to state that the order is that which is defined in the code.

Question 79

If you've reduced a N:1 multiplexor using pipelining how do you calculate the new number of combinational logic blocks for the critical path calculations?

Answer 79

log₂(N)

Question 80

What does the **logic** type represent?

Answer 80

The **logic** type is used in SystemVerilog to model signals in digital circuits – it has _4 possible values_ 0, 1, X (unknown) and Z (high impedance).

Question 81

Block diagram of ADC-SAR

Answer 81

Question 82

Critical Path: Sketch a timing diagram for the critical path, and calculate the maximum clock frequency. 2018 - q2 - c)

Answer 82

Question 83

Explain the changes to the SystemVerilog code that are required to make the reset synchronous?

Answer 83

The sensitivity list for the always\_ff block contains posedge reset, meaning that the block will be active when the reset goes high whatever the state of the clock. Removing posedge reset from the sensitivity list will ensure that the reset only triggers on the positive edge of the clock:

Question 84

Switch Model Circuit Diagram 2018 - q3 - a

Answer 84

Question 85

When determing the time of the critical path, what timing parameters should you be looking at?

Answer 85

propagation delays and setup times as seen in the past paper questions until now...

Question 86

Specifically what does the third line do?

Answer 86

as you can see there is a \*() with the pointer address +2 inside. with the \*(address+2) you are saying you want the value two places down from addresses poisition.

Question 87

A digital circuit is required which adds four 8-bit unsigned numbers in a single clock cycle with registers on every input and output. (a) How many bits are required in the output?

Answer 87

An 8-bit unsigned number can take values from 0 to 255, so the maximum output is 1020 which can be expressed as a _10-bit number_.

Question 88

Describe the function of the **initial** block within test bench code and how it differs from **always\_ff** and **always\_comb** blocks used in synthesisable code

Answer 88

A test bench is a code used to _test a synthesisable module_ not a representation of actual digital circuits. **always\_ff** blocks _model edge triggered logic_ such as flip-flops and **always\_comb** blocks _model combinational logic_ in which _the output changes whenever the inputs change_. In simulation, **initial** blocks are _executed sequentially_ like a software code (**always\_ff** and **always\_comb** on the other hand do not). They _define signal changes_ and other actions that occur at distinct points in time. **Initial** blocks always start executing at the start of simulation time and continue until all the instructions are completed.

Question 89

Can the Event1/fnc3() of state 1 be considered a unique transition?

Answer 89

yes if it ins't found anywhere else.

Question 90

How do you find the unique events of a FSM?

Answer 90

count up all the unique transistions

Question 91

C programming: what does this mean?

Answer 91

creates a 2x3 matrix called statetable of type char