Exam Prep Deck Flashcards
(91 cards)
What factors limit the increased throughput that can be obtained using pipelining in complex designs such as a microprocessor data path?
Diminishing returns with each pipeline stage added due to the setup and propagation times of the flip- flop. Also, complex circuits such as the microprocessor data path have dependencies between the pipeline stages (data and control hazards) which require additional logic and delays to overcome and hence do not achieve the expected speed up.
Question iii)
The critical path length is now (3 x RAM delay) + (3 x mux delay) = (3 x 500ps) + (3 x 50ps) = 1650 ps
The minimum clock period = critical path + setup + clock-to-Q = 1650ps + 50ps + 70ps = 1770 ps
Maximum clock frequency = 1/2870ps = 565MHz
Briefly describe the verification process for digital designs
The desired behaviour of the digital circuit is captured in a HDL (hardware description language_)_ such as SystemVerilog. A set of test inputs or “test vectors” are generated which cover all the expected operating conditions of the circuit. Another HDL code, the test bench, is used to apply the test vectors to the circuit in simulation and the outputs are captured. A software model of the circuit behaviour is also created. The HDL simulation and software model outputs are compared to detect logical errors in the HDL code before synthesis starts. This process reduces the probability that defects will be present in the final product.
Architecture
Price lowest to highest: ASIC -> Microprocessor -> FPGA
Define Setup error
The input to a sequential element such as a flip-flop must be stable a certain time before the clock edge, known as the setup time. A setup error occurs when this condition is not met.
Work out DCO tune as an integer?
- Pick a range(DCORSEL).
- Select the desired frequency within that range (FDCOnom).

Explain the following terms in the context of the digital design process.
(i) Constraints
(ii) Recurring costs
(iii) Non-recurring costs
Constraints: requirements which have been identified for the design, for example, minimum clock frequency, maximum delays, maximum area etc.
Recurring costs: costs which have to be paid each time a chip is manufactured, including fabrication, testing and packaging
Non-recurring costs: costs which must be paid before a chip can be manufactured, including design and tooling costs
Specify the contents of the RAM blocks in a CLB to create a 2:1 multiplexer
Assign I0 and I1 on the 16x1bit RAM to be the 2 bits of D. Assign I2 on the 16x1bit RAM to be S, I3 is a “don’t care”.
A single CLB can represent the mux with the following RAM entry:
(to get the address values just combine all the row elements from left to right.
I0 is 4 zeros followed by 4 1s
I1 is alternating sets of pairs
I2 is simply alternating going down.
I3 is just x’s for all the bits.
(i) Explain how the current state variable is updated using the state table implementation approach in c code.

The new state is simply updated using array indexing where the row index is the event value and the column index is the current state. The updated state is given by the value at this memory location.
state = statetable[event][state];
4:1 multiplexor a behavioural style with case statements
Define what is meant by static timing analysis.
In static timing analysis, the delay of every combinational path between sequential elements is calculated. These are used to assess whether each sequential element meets it’s setup and hold conditions under a set of timing constraints such as clock frequency and jitter.
Write C code to implement the action handler for the actiontable, assuming there is a current state variable currentstate and an event variable event. You can assume the action functions: fcn0() … fcn3() are already defined.
Do q b)
Sketch the block diagram of the circuit in terms of the adder and flip-flop cells.
ii)


What is a precision ADC?
module that can achieve over 16bit precision using software oversampling, up to 1 Mbps sampling rate with differential and single ended inputs.
Describe the concept of corner analysis and how it would be applied to variations of Vdd across a digital integrated circuit.
Corner analysis ensures that a high proportion of the chips fabricated will work across all the process and environmental variations. It involves carrying out static timing analysis at the extreme operating conditions or “corners”.
In the case of power supply variation, gates with a low value of Vdd will run slow and hence be more susceptible to setup errors. Gates with high Vdd will run fast and be more susceptible to hold errors. A corner analysis including Vdd variation could include static timing analysis with (1) low Vdd, slow transistors due to process variation and high temperature to ensure that setup errors do not occur and (2) high Vdd, fast transistors and low temperature to ensure that hold errors do not occur.
When using an input pin on a microcontroller as an analogue input what will the input impedance be?
The pin will be in the high impedance state
Explain how Pulse Width Modulation (PWM) is used to control the speed of the motors and describe how it is implemented in microcontroller hardware.
What are the key words/terms you need to remember
PWM is a method of producing an analogue voltage level from a digital output. A PWM signal consists of a periodic pulse train whose frequency is much higher than the frequency of the device or system that is been driven. The signal amplitude is then adjusted by varying the pulse duration or duty cycle. The output waveform is then lowpass filtered, either by a specific low pass filter or simply by the response time of the system that is been stimulated, to produce the analogue waveform. In a microcontroller this is implemented using a timer/counter and two counter compare registers. The timer/counter is clocked at a certain rate 𝑓𝑐𝑙𝑘 using a divided version of the system clock. One counter compare register is used to set the maximum count and hence the period of the PWM signal i.e. 𝑇 = 𝑀𝑎𝑥𝐶𝑜𝑢𝑛𝑡 / 𝑓𝑐𝑙𝑘 . The other compare register is used to set the duty cycle and hence the output amplitude.
Key words/terms to remember: analogue voltage level, periodic pulse train, duty cycle, low pass filter, timer/counter, counter compare registers, maximum count, output amplitude
Explain what is meant by Dennard scaling in the semiconductor industry.
Define pipelining
Partitioning a circuit or algorithm into multiple stages, separated with sequential elements, in order to increase the clock speed and throughput.
Pipelining involves splitting up the functions performed by the combinational logic into separate functions and inserting sequencing flip-flops or registers into the path. Because the delay of the combinational logic in each pipeline stage has been reduced, the clock frequency can be increased or supply voltage can be reduced to save power.
(iii) What is the maximum throughput of the circuit, i.e. the number of sum outputs generated per second?

The minimum clock period is the sum of 3 adder cell propagation delays and the flip-flop setup and clock-to-Q propagation delays.
Minimum period = (3*300ps)+50ps+65ps = 1015ps.
The maximum clock speed or throughput is, therefore, 1/1315ps = 985MHz
Note that they cheekily put maximum propagation delay of adder cells outside of the table.
16 bit vs 8 bit
The 16-bit processor will be two times faster.
Define: Non-recurring costs
Non-recurring costs are any costs which must be paid before any products can be fabricated including d_esign engineering costs_, prototyping, product–specific equipment required for design, product-specific manufacturing equipment such as photomasks and packaging tools
Define Standard Cell Library
A set of predefined characterized layouts of basic logic functions such as AND, OR, invert, flip-flop, latch, multiplex etc. The cells have fixed height and variable width to allow a circuit layout on a regular grid, speeding up development times.
















