Fetch Decode Execute Flashcards

(10 cards)

1
Q

ALU

A

arithmetic logic unit- performs arithmetic and logic calculations

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2
Q

program counter

A

holds the address of the next instruction to be executed

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3
Q

control unit

A

responsible for controlling various components of the processor

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4
Q

CIR

A

current instruction register- holds the instruction that is currently being executed by the processor

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5
Q

MAR

A

memory address register- holds the memory address of a memory location that is to be read and written to

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6
Q

MBR

A

memory buffer register- holds the contents of a memory location that has been read from

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7
Q

status register

A

contains a number of bits the values of which can
change to indicate the occurrence of an interrupt

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8
Q

explain the stages of the fetch cycle

A

In the fetch stage of the cycle, the next instruction to execute is retrieved from main memory.
1. The content of the PC is copied to the MAR
2. The content of the MAR is transferred to main memory by the address bus
3. The instruction is sent from main memory to the MBR by the data bus
4. The PC is incremented by one
5. The content of the MBR is copied to the CIR

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9
Q

explain the stages of the decode cycle

A

In the decode stage of the cycle, the fetched instruction is
decoded.
1. The content of the CIR is decoded by the control unit
2. The decoded instruction is split into two parts: opcode
and operands

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10
Q

explain the stages of the execute cycle

A

The instruction is carried out in the execute stage of the cycle.
1. Any data required by the instruction that isn’t present in registers is fetched
2. The instruction is carried out
3. Results of any calculations are stored in general purpose registers or main memory

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