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Hardware Flashcards

1
Q

RME: definition and one thing

ARM

A

Realm management extension
Architecture extension for Arm’s confidential compute architecture

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2
Q

SME

ARM

A

Scalable matrix extension

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3
Q

ICC_IAR

GIC

A

Interrupt acknowledge register

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4
Q

MTE: How do enable tag checking for a memory region in stage 1?

A

PTE index to MAIR with tagged attribute

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5
Q

What’s WIMG?

XNU

A

Memory attributes in pmap such as cache abilities and MTE

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6
Q

POE2

ARM

A

Permissions overlay extension 2

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7
Q

MTE: tag to memory ratio

A

4 bit tag for every 16 bytes of physical memory

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8
Q

MTE: read, write and generate tag instructions

A

LDG, STG, IRG

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9
Q

AMX

Apple Hardware

A

Apple matrix extension

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10
Q

CPMU: definition and four features

Apple Hardware

A

Core performance monitor unit
Cycle counter
Filtered event counter
Event sampling
Counter overflow exception

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11
Q

UPMU: definition and description

Apple Hardware

A

Uncore performance monitor unit
Counting events in uncore blocks such as LLC
counter overflow exception

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12
Q

CLPC: definition, description, aka

Apple Tech

A

Closed loop performance control
System power management and performance control
Also known as AON_PMU

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13
Q

H16 Mac Chips

A

G: Donan
Brava

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14
Q

H17 Mac Chips

A

G: Hydra
Sotra

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15
Q

H18 Mac Chips

A

P: Thera
A: Tilo
G: Komodo

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16
Q

Apple silicon high density compute server 2025: code, chip, storage, NIC, ancestor

A

J226
Replaces J126
32x H17G
1 TB storage
200 Gbps NIC

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17
Q

HDR: definition and description

Graphics

A

High dynamic range
Enable a monitor to display a broader spectrum of colors and contrasts

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18
Q

ARM system ready

A

Measures compliance to a set of hardware and firmware standards

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19
Q

GICH_ELRSR: description

ARM GIC

A

Empty list register status register

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20
Q

AVX

Intel Architecture

A

Advanced vector extension

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21
Q

CPP RCTX

ARM

A

Cache prefetch prediction restriction by context

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22
Q

CFP RCTX

ARM

A

Control flow prediction restriction by context

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23
Q

ARM： FEAT_LOR - definition and description

A

Limited ordering regions
Allow large systems to perform special load and store instructions that provide order for a specified region of physical memory

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24
Q

POE: how to identify code and data spatially

A

Translation of the VA on a per page granularity

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25
POE: how to identify code temporally
TIndex
26
POE: 3 spatial access enforcement
What code can run What code can read or write what data What code can execute which instructions or access which system registers
27
POE: POIndex: definition and description
Permission overlay index Specified in stage 1 translation table descriptor
28
POE: FPOIndex: definition and description
Fetch POIndex The POIndex from the translation of current PC VA
29
POE: DPOIndex: definition and description
Data POIndex The POIndex from the translation of the VA for the target of a memory accessing instruction
30
POE: TIndex
Temporal index
31
POE: POTIndex: definition and description
Permission overlay table index Index into DPOT and TTT
32
POE: FGDTIndex: definition and description
Fine grained dynamic trap index Select which FGDT register to use
33
POE: IRT: definition, 2 input, 3 output
Instruction region table In memory table that generates execute permission, FGDTIndex and POTIndex from TIndex and FPOIndex
34
POE: DPOT: definition and description
Data permission overlay table Describes stage 1 data read and write permission subtractions from POTIndex and DPOIndex
35
POE: TTT: definition and description
TIndex transition table Describe the permitted transitions of TIndex
36
POE: FGDT: definition and description
Fine grained dynamic trap Restrict instruction and system register accesses
37
POE: PLB
Permission look aside buffer
38
POE: LDSTT_ELx
Value of FPOIndex to be used by load and store unprivileged instructions
39
POE: TPS: D2
Thread private state check Restrict any access by the thread to a thread private page that is outside its min and max bounds
40
RDMA: d2
Remote direct memory access Access from the memory of one computer into that of another without involving either one’s operating system
41
Context synchronization event: what, how 3 | ARM
Guarantee visibility of any system register change ISB exception entry and return Exit from debug state
42
ARM: S2PIE: definition
Stage 2 Permission Indirection Enable
43
ARM: TPS: d2
Thread private state Prevent access to a thread private page that is outside its min and max bounds
44
ARM: BTI2: where, three requirements
Enhanced guarded page Link register set by instruction before BTI c landing pad for branches landing pad for returns
45
ARM Memory: Uncached: what and when
Provides real time guarantees as the memory is never cached Available in H12+
46
ARM memory: non cached
Write combined memory that reduces likelihood of cache snooping
47
RGSR_EL1 | ARM MTE
Random (allocation tag) generator seed register
48
GCR_EL1 | ARM MTE
Tag control register
49
TFSR_EL1 | ARM MTE
Tag fault status register
50
#ARM VMSA Locks | Purpose
Control the MSR write-access to various ARM ISA system registers.
51
APRR: definition | Apple Hardware
Access protection restriction register
52
Granule protection table | ARM
Tracks whether a page is used for realms, trust zone or normal world
53
H19 SoC Names
P/iPhone: Borneo A/iPhone: Banda ASM: Andros G: Delos
54
ISA: TUNIMP
Trap unimplemented PSTATE or instructions
55
FEAT_NV2p1 | ARM
Retain bits that are used in EL2 but reserved in EL1
56
FEAT_ECV: what, 2 benefits for our virtualization stack | ARM
Enhanced counter virtualization offset between guest and host view of physical time Direct physical timer interrupt to vGIC
57
FEAT_UINJ | ARM
Provide higher privilege software with a future proofed mechanism to inject an Undefined Instruction exception into lower privilege software
58
S1PIE | ARM
Arm indirection permission scheme
59
ERETAA/ERETAB compared to ERET: what, input
Authenticate the address in ELR SP as modifier, IA/IB as πŸ”‘
60
PACGA: what, 3 inputs, contrast with PACIx
Compute pointer authentication code for an address Address in the first source register, modifier in the second source register, generic πŸ”‘ Same PAC bits regardless of TBI and TxSZ
61
Three Apple mode PAC πŸ”‘ diversification
Host EL2/0: HMKEY Guest EL1/0: VMKEY Per-key 4 bit value
62
ARM breakpoint slip avoids 4 things
Replace BRK with original instruction, and vice versa Stop other threads which share the breakpoint Create instruction pages Perform instruction specific adjustments (BL)
63
BTI: purpose, function, integration | ARM
Purpose:prevent branch target injection Function: Requires indirect branches to land on valid BTI markers; Integration: Works with guarded pages and Pointer Authentication
64
FEAT_CMOW
control for cache maintenance permission
65
FEAT_ASID2
Concurrent use of two ASIDs
66
FEAT_ETS3
Enhanced translation synchronization v3
67
FEAT_STEP3: d2
Enhanced software step extension Software step executes stuffed instruction instead of the original instruction at that VA
68
ARM: RAS
Reliability, availability and serviceability
69
FEAT_NV3 | two benefits
Avoid unnecessary trapping of ERET instructions under nested virtualization Avoid unnecessary trapping of TLBI instructions under nested virtualization

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