Input/Output (I/O) Interfacing Flashcards

1
Q

a subsystem of components that moves coded data between external devices and a host system, consisting of a CPU and main memory.

A

Input/Output (I/O)

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2
Q

depends upon the size of computer and the peripherals connected to it

A

I/O Organization

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3
Q

An external device attached to the computer by a link to an I/O module

A

Peripheral Device

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4
Q

Common Input/Output devices

A

Monitor
Keyboard
Mouse
Printer
Magnetic tapes

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5
Q

Three categories of external/peripheral device

A

Human readable
Machine readable
Communication

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6
Q

A type of peripheral device suitable for communicating with the computer user

A

Human readable

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7
Q

A type of peripheral device suitable for communicating with equipment, such as sensors and actuators

A

Machine readable

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8
Q

A type of peripheral device suitable for communicating with remote devices such as a terminal, a machine readable device, or another computer.

A

Communication

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9
Q

I/O subsystems

A

Blocks of main memory
Buses
Control modules
Interfaces to external components
Cabling or communications links

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10
Q

exact form and meaning of the signals exchanged between a sender and a receiver

A

protocol

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11
Q

the receiver must acknowledge the commands and data sent to it or indicate that it is ready to receive data. This protocol exchange is called

A

handshake

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12
Q

Signals comprised by protocol

A

command signals
status signals
data-passing signals

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13
Q

serve as interfaces between the CPU and its peripherals

A

Dedicated I/O modules

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14
Q

provides a method for transferring information between internal storage (such as memory and CPU registers) and external I/O devices.

A

Input – Output Interface

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15
Q

special hardware components between the CPU and peripherals to supervise and synchronize all input and out transfers.

A

Interface Units

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16
Q

I/O Module Function that coordinates the flow of traffic between internal resources and external devices.

A

Control and timing

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17
Q

I/O Module Function that involves command decoding data status reporting address recognition.

A

Processor communication

18
Q

I/O Module Function that detect and reports transmission errors

A

Error detection

19
Q

I/O Module Function that performs the needed buffering operation to balance device and memory speeds.

A

Data buffering

20
Q

I/O Module Function that involves commands, status information and data.

A

Device communication

21
Q

It defines the typical link between the processor and several peripherals.

A

I/O BUS and Interface Module

22
Q

four types of I/O commands

A

Control
Test
Read
Write

23
Q

I/O Command that is used to activate a peripheral and tell it what to do

24
Q

I/O Command that is used to test various status conditions associated with an I/O module and its peripherals.

25
I/O Command that causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral.
write
26
I/O Command that causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer
read
27
the address and data lines from the CPU can be shared between the memory and I/O devices
Shared I/O arrangement
28
Devices and memory share an address space. I/O looks just like memory read and memory write
Memory – Mapped I/O
29
Separate address spaces. Need I/O or memory select lines.
Isolated I/O
30
different I/O techniques
programmed i/o interrupt-driven i/o Direct Memory Access (DMA)
31
refers to data transfers initiated by a CPU under driver software control to access registers or memory on a device. sometimes called polled I/O.
Programmed I/O
32
Instead of the CPU continually asking devices whether they have input, the devices tell the CPU when they have data to send
Interrupt-Driven I/O
33
The circuit that handles interrupt signals from all I/O devices in the system
intermediary interrupt controller
34
recognizes interrupt signals from any of its attached devices, it raises a single interrupt signal that activates a control line on the system bus
Interrupt controller
35
Type of interrupt where the signal for the processor is from external device or hardware
Hardware Interrupt
36
The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor
Maskable Interrupt
37
The hardware which cannot be delayed and should process by the processor immediately
Non Maskable Interrupt
38
It is a software interrupt caused by the software instructions
normal interrupt
39
It is a software interrupt caused by unplanned interrupts while executing a program
exception
40
a special hardware that manages the data transfers and arbitrates access to the system bus.
Direct Memory Access Controller
41
device can transfer data directly to and from memory, rather than using the CPU as an intermediary.
Direct Memory Access
42
DMA controller three registers
address register data count register control logic