L15 - Networking Flashcards

1
Q

What is the communication hierarchy in a data center?

A

Server NIC –> Top of the Rack Switch –> Cluster Switch

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
2
Q

What are 4 interface mechanism for networking?

A
  1. Register and queue based device interface
  2. Memory mapped I/O, virtual memory, user/kernel modes
  3. Direct memory access (DMA)
  4. Interrupts and polling
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
3
Q

What is DMA?

A

separate engine to transfer blocks of data between an I/O device & memory (without involving the CPU)

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
4
Q

How does DMA work?

A
  1. CPU describes the transfer to the DMA engine (source address, destination address, transfer size, type)
  2. DMA engine performs memory/IO read/writes
  3. DMA engine completes transfer by sending interrupt to CPU

note: CPU can execute other code during the DMA transfer

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
5
Q

What are the advantages of DMA?

A

It decouples data transfer from processing and thus:

  1. CPU does not need to copy data to/from device
  2. Doesn’t pollute CPU cache
  3. Can be processed when the CPU (or OS) decides
  4. Higher-performance: CPU and device work in parallel
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
6
Q

When is DMA disadvantageous?

A

for very small transfers: higher setup overhead

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
7
Q

Steps of DMA for ‘writing’?

A
  1. Allocate DMA-able buffer with packet data
  2. Write DMA descriptor to NIC
  3. NIC DMA engine copies data for transmission
  4. TX completion notification (interrupt)
  5. Deallocate buffer
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
8
Q

Steps of DMA for ‘reading’?

A
  1. Allocate buffer for received packet
  2. Write DMA descriptor to NIC
  3. NIC DMA engine copies data to host
  4. RX notification to host (interrupt)
  5. Forward received packet to user application
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
9
Q

What are the possible ways of solving DMA and cache inconsistencies?

A
  1. CPU can map DMA buffers non-cacheable
  2. Cache can “snoop” DMA bus transactions (but doesn’t scale beyond small SMP systems)
  3. OS can explicitly flush/invalidate cache regions
  4. Direct cache access
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
10
Q

What are the consequences of using physical addresses for DMA?

A

If physical address, DMA engine does not need to worry about translation. But there are a few things to watch out for:

  • Need to use pinned addresses (cannot remap for non-IO use)
  • The physical addresses in a multi-page transfer may not be contiguous –> need to break up into page-size DMA transfers
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
11
Q

What are the consequences of using virtual addresses for DMA?

A

DMA engine needs to handle translation.

Particularly useful when we have virtual machines sharing I/O device.

How well did you know this?
1
Not at all
2
3
4
5
Perfectly