L5-6 Combinational Logic & Sequential Logic Flashcards
(28 cards)
Define combinational circuits.
Outputs depend only on current inputs. Memoryless.
Define sequential circuits.
Outputs depend on both current and previous values of the inputs. Circuits with memory.
Define timing specification.
Specifies the lower and upper bounds on the delay from input to output.
Define functional specification.
Expresses o/p values in terms of current input values.
Define minterm.
Product involving all of the inputs to the function.
Define maxterm.
Sum involving all of the inputs to the function.
What do multiplexers (mux) do?
Allow user to choose between multiple inputs.
-2^k input bits and k select bits.
What do decoders do?
Decoders select one o/p bit to be high and the rest to be low. k input bits produce to k output bits.
How do you create a simple bistable element?
Connect two NOT gates (inverters) back-to-back/ criss-cross, with feedback. //This will produce a sequential circuit//
Problems with bistable circuits?
Can’t be reset/ no input/ no user control.
What does the S-R latch change about the simple bistable circuit?
Replaces NOT gates with NOR gates and adds a set and reset for user control.
What happens when S-R Latch is reset and set to 0?
Output, Q, will equal Qprev i.e. memory state.
What happens when S=1 and R=1?
The system can’t choose whether the output will be 1 or zero and states begin to contradict. Don’t set both to 1.
How would you improve the SR Latch?
Make it a D-Latch. This will prevent S and R being 1 simultaneously.
What does ‘D’ do in the D-Latch?
Controls what the state should be.
What does ‘CLK’ do in the D-latch?
Controls when the state should change.
What happens when the CLK is set to 0?
System becomes opaque and D cannot be set.
What are the problems with the D Latch?
Updates its state continuously when CLK=1. //It’s often useful to update state only at specific time//
How would you improve D-Latch?
Make it a D-Flip flop.
What is a D-FF composed of?
Back-to-back D latches controlled by complementary clocks.
How does a D-FF work?
CLK is set to 0 so master is transparent and slave is translucent. Signal is set as D=1 and this propagates to Q then through to N1,
CLK is then set to 1 so master becomes opaque and slave transparent, so N1 propagates from D to Q in the slave FF.
Therefore, what was copied into Q is what was there in D when the CLK went from 0 to 1.
What is the rising edge time?
The moment when the CLK rises from 0 to 1 and when the value gets copied from D to Q in the DFF.
What are registers composed of?
N-bit register is a bank of N flip-flops that share a common CLK.
Problems for sequential circuits?
- ) Astable circuits- i/p and o/p keep changing.
- ) Race conditions- delays through different components mean information doesn’t get passed to the tight place in time (or passed too fast)
- The o/p will become stuck.
