Lecture 3 Memory Cache

Question 1

Background (Overview)

Answer 1

• The document discusses various cache optimizations aimed at improving memory access time and reducing miss rates.
• It builds upon the memory hierarchy concept, where smaller, faster caches store subsets of data from larger, slower memory.

Question 2

Problem (Motivation) (5 Problems)

Answer 2

• Basic cache designs have limitations in terms of hit time, miss rate, power consumption, and complexity.
• Larger cache line sizes can reduce compulsory misses but increase capacity and conflict misses.
• Larger total cache capacity reduces the miss rate but increases hit time and power consumption.
• Higher associativity reduces conflict misses but increases hit time and power consumption.
• Prioritizing writes over reads can increase miss penalty.

Question 3

Solution (Basic Cache Optimizations)
(LLHHG)

Answer 3

Basic Optimizations:

• Larger Cache Line Size: Reduces compulsory misses.
• Larger Total Cache Capacity: Reduces miss rate.
• Higher Associativity: Reduces conflict misses.
• Higher Number of Cache Levels: Reduces overall memory access time.
• Giving Priority to Read Misses Over Writes: Reduces miss penalty.

Question 4

Solution (Advanced Cache Optimizations)
(SWPNV)

Answer 4

Advanced Optimizations:

• Small and Simple First Level Caches: Improves access time.
• Way-Predicting Caches: Improves hit time by predicting a way to prime the cache hardware.
• Pipelined Cache Access: Improves bandwidth.
• Non-Blocking Caches: Enables hits before previous misses complete.
• Victim Cache: Reduces conflict misses in direct-mapped caches.