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Memory Flashcards

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1
Q

Physical Memory AKA

A

RAM

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2
Q

Memory needs to be

A

subdivided

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3
Q

Memory hierarchy

A

Registers, cache, main memory, solid state disk, magnetic disk

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4
Q

Memory management is an _ task under _

A

optimization task under constraints

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5
Q

Fixed-partition Allocation divides memory into

A

Fixed-size partitions

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6
Q

Fixed-partition allocation, each partition contains

A

exactly one process

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7
Q

In fixed-partition allocation, the degree of multiprogramming is bound by

A

the number of partitions

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8
Q

In fixed-partition allocation, what happens when a process terminates

A

The partition becomes available for other processes

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9
Q

Internal Fragmentation

A

Allocated memory may be slightly larger than requested memory

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10
Q

internal fragmentation size difference

A

is memory internal to a partition but not being used

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11
Q

Variable-partition scheme (dynamic) process

A

When a process arrives, search for a hole large enough for this process

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12
Q

Variable-partition scheme (dynamic) hole definition

A

Block of available memory; holes of various size are scattered throughout memory

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13
Q

In Variable-partition scheme (dynamic), how much memory is allocated

A

Only as much memory as needed

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14
Q

in Variable-partition scheme (dynamic), what does the OS maintain information about?

A

Allocated Partitions
Free partitions (hole)

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15
Q

External Fragmentation

A

Total memory space exists to satisfy a request, but it is not contiguous

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16
Q

What could fixed-partition allocation lead to?

A

Internal Fragmentation

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17
Q

What could Variable-partition scheme (dynamic) lead to?

A

External Fragmentation

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18
Q

How to reduce External Fragmentation?

A

Compaction

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19
Q

External Fragmentation 50% rule

A

number of holes = .5 * number of occupied blocks

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20
Q

Compaction

A

Shuffle memory contents to place all free memory together in one large block

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21
Q

Compaction is only possible when? and at done when?

A

It is only possible if relocation is dynamic and is done at execution time

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22
Q

First-fit

A

Allocate the first hole that is big enough

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23
Q

Best-fit

A

Allocate the smallest hold that is big enough

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24
Q

Best fit must do what?

A

Search entire list, unless ordered by size

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25
What will best-fit produce?
The smallest leftover hole
26
Worst-fit
Allocate the largest whole
27
Next-fit
Starts each search at the point of the last allocation (round robin)
28
What must worst-fit do?
Search the entire list
29
Worst-fit produces
The largest leftover hole
30
Which dynamic storage-allocation is fastest?
First-fit
31
Physical memory (RAM)
Hardware Structure consisting of a linear sequence of words
32
Word
Fixed size unit of data, usually 4 bytes
33
Logical Address Space
An abstraction of physical memory, consisting of a sequence of imaginary memory locations [0: m-1]
34
Source Module
A program or program component written in a symbolic language like C or assembly, that must be translated by a compiler or assembler into executable machine code
35
Source Module to object module
Translation
36
Object module(s) to Load Module
Linking
37
Object Module
The Machine language output of a compiler or assembler from a source module.
38
Load Module
A program or combination of programs in a form ready to be loaded into main memory and executed
39
Load Module on disk to Load module in memory
Loading
40
What are system libraries
collections of precompiled and reusable code that provide foundational functionality to the operating system and applications
41
Addresses in a source program are usually
Symbolic
42
What does a compiler do to these symbolic addresses
A compiler binds these symbolic addresses to relocatable addresses
43
What does the linkage editor or loader do to the relocatable addresses
It binds the relocatable addresses to absolute addresses
44
What does each binding do
It maps from one address space to another
45
Source program address example
int count;
46
Relocatable address example
100 bytes from the beginning of this module
47
Each process has
A separate memory space
48
Which two registers provide address protection between processes
Base Register Limit Register
49
Absolute address example
74014
50
Memory-Management Unit (MMU)
Hardware Device that maps logical to physical address
51
Base Register
Smallest legal address space
52
Limit Register
Size of the legal range
53
In MMU, what is special about the value in the relocation register (base) register?
It is added to every address generated by a user process at the time it is sent to memory
54
Which program deals with logical addresses?
User Program
55
Does the user program ever see the real physical address?
No
56
What does the CPU hardware compare?
Every address generated in user mode with the registers
57
What will an attempt to access other processes' memory do?
It will be trapped and cause a fatal error
58
Logical Address
An integer in the range [0: m-1] that identifies a word in a logical address space
59
What do the compiler/assembler and linker assume the logical address space start with at load time?
Address 0
60
Relocation
The act of moving a program component from one address space to another
61
Static relocation
Binds all logical addresses to physical addresses prior to execution
62
Dynamic relocation
Postpones the binding of a logical address to a physical address until the addressed item is accessed during execution
63
Segmentation
Memory-management scheme that supports user view of memory
64
A program is a collection of
segments
65
two tuple in each logical address
66
Segment table
Maps two-dimensional physical addresses
67
Each table entry in segment table has
Base - contains the starting physical address where the segments reside in memory limit - specifies the length of the segment
68
Segment-table base register (STBR)
points to the segment table's location in memory
69
Segment-table length register (STLR)
indicates the length (limit) of the segment
70
Sharing of segments
Share code/editor segment but have different data segment
71
Can physical address space of a process be noncontiguous?
Yes
72
[physical] frames
divide physical memory into fixed-size blocks
73
[logical] pages
Divide logical memory into blocks of same size
74
How to run a program of size n pages?
find n free frames and load program
75
Paging address translation is dividing address generated by cpu into
Page number (p) Page offset (d)
76
Page number (p)
Used as an index into a page table which contains base address of each page in physical memory
77
Page offset (d)
Combined with base address to define the physical memory address that is sent to the memory unit
78
Paging
Noncontiguous allocation of memory
79
Shared pages -- shared code
One copy of read-only (reentrant) code shared among processes Must appear in the same location in the logical address space of all processes
80
Shared pages -- private code and data
Each process keeps a separate copy of the code and data Can appear anywhere in the logical address space
81
Page table is kept in
main memory
82
Page table base register (PTBR) points to
page table
83
Page-table length register (PLTR) indicates
size of the page table
84
What two memory accesses does the paging scheme in every data/instruction access require?
One for page table and one for data/instruction
85
How can the two memory access problem be solved?
Fast lookup hardware cache called associative memory or translation lookaside buffers (TLBs)
86
How big is TLB?
64 to 1024 entries
87
What happens on TLB miss
Value is loaded into the TLB for faster access next time
88
How to solve TLB problem when switching processes?
Need to flush at every context switch Or store address-space identifiers in each TLB entry to uniquely identify each process and provide address-space protection for that process
89
How much faster is TLB than memory access
An order of magnitude
90
Hierarchical Page Tables
Break up the logical address space into multiple page tables
91
Two-level paging: logical address is divided into
Page number Page offset
92
Two-level paging: Page number is divided into
Page table index (within the outer page directory) Page index (within the inner page table)
93
Intel IA-32 Architecture support both
Segmentation and segmentation with paging
94
Who generates logical address?
CPU
95
Where is selector given to?
Segmentation unit
96
What does segmentation unit produce?
Linear Address
97
What is linear address given to?
Paging unit
98
What does paging unit produce?
Physical Address in main memory
99
What can be the size of each page
anything of the power of 2

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