Midterm 1- Slide Decks A3-A4

Question 1

What are the sub-parts of the CPU?

Answer 1

registers, ALU, control

Question 2

What 4 types of instructions can all CPUs perform?

Answer 2

1. Data movement instructions(transfer data from memory to CPU, and from CPU to memory, or between two registers)
2. Arithmetic & logic operations on data(ADD, SUB, AND, XOR, NEG)
3. Program sequencing and control instructions (unconditional/conditional branches)
4. Input/output transfers(transfer data from device to memory, or memory to device)

Question 3

How is a Read from performed?

Answer 3

• memory retrieves content at address given by CPU
• value in memory does not change (READ does not change bit string EVER!)

Question 4

How is the Write memory instruction performed?

Answer 4

• Memory overwrites contents at address given by CPU with data given by CPU
• value overwritten is LOST (bits change unless it has been preserved somewhere else before being overwritten

Question 5

Which register in the CPU is used to hold the address of the instruction being executed?

Answer 5

Program counter (PC)

Question 6

Which register in the CPU holds the instruction being executed (the bit string with the encoded instruction)?

Answer 6

Instruction register (IR)

Question 7

What kind of program converts assembly language to machine language?

Answer 7

The assembler

Question 8

What is a RISC Processor?

Answer 8

RISC processors have one-word instructions and require arithmetic operands to be in CPU registers; so in RISC, can’t have: add 100, 200 (adding words at addresses in memory). RISC processors have smaller instruction

Question 9

What is a CISC Processor?

Answer 9

CISC processors have variable length instructions (many multi-word instructions) and allow ALU operands directly from memory

Question 10

Intels are what type of CPUs?

Answer 10

CISC processors

Question 11

Which type of CPUs are ARMs and Mac M1, M2, and M3?

Answer 11

RISC processors

Question 12

Which of the two types of processor architectures is called load/store?

Answer 12

RISC

Question 13

How many assembly language instructions typically correspond to a single statement in a high-level language (such as Java, C++, or C)?

Answer 13

Multiple assembly language instruction

Question 14

When can the address in the PC register be incremented to the address of the next instruction?

Answer 14

After the address has been sent to memory, so that the instruction can be read/fetched from memory.

Question 15

Which kinds of instructions in the CPU are used to execute if or else (or loop) statements in a high-level language?

Answer 15

Branch/Jump instructions

BLZ- goes to label in instruction to execute next instruction if last ALU result was less that 0.

BR- will go to label to execute next instruction without any condition

Question 16

What is the Processor Status Register (or PSR)?

Answer 16

Four 1 bit flags in the PSR that are used by processor to store information about the result of executing an ALU instruction

Question 17

What four flags does the PSR have?

Answer 17

S - Sign flag: Set to 1 by processor of result of last ALU operation was negative (msb of result is 1); otherwise set to 0
Z - Zero flag: Set to 1 by the processor if the result of the last ALU operation was 0; otherwise eat to 0
C - Carry flag: Set to 1 if result of last instruction generated a carry of 1; otherwise set to 0
O - Set to 1 if last two carries are different, otherwise set to 0.

Question 18

What are labels used for in assembly language?

Answer 18

To mark addresses of data or instructions in a program

Question 19

Do labels occupy any space in memory? Why or why not?

Answer 19

Labels use no space in memory because they are NOT data

Question 20

Which built-in data structures does the CPU recognize?

Answer 20

None. There are NO built-in data structures which the CPU recognizes

Question 21

What is a subroutine (function/procedure/method)?

Answer 21

Function: Some task may have to be done many times using different sets of data

Procedure: Implement task in one block of instructions; this is the subroutine

Method: We use a subroutine call. Will return to the instruction where the call was made

Question 22

How is a subroutine called?

Answer 22

Caller subroutine puts parameters for callee in frame of callee. When called, address of next instruction after call will be pushed onto stack

Question 23

How is a subroutine call different from a branch?

Answer 23

A return address must be saved

Question 24

In what two ways can the return address be saved?

Answer 24

Single link register and stack

Question 25

Which way of saving a return address has a limitation on the number of subroutine calls which can be made before returning to the original calling subroutine?

Answer 25

**Stack, since the size is fixed and it has a limit**. We do not have an infinite amount of memory

Question 26

Besides being used to save a return address, what other kinds of data related to a subroutine call can a stack be used for?

Answer 26

Parameters and return value

Question 27

How many instructions in assembly language correspond to a single machine language instruction?

Answer 27

One assembly instruction always per machine language instruction

Question 28

Does every type of CPU (Intel, ARM, Mac M1, SPARC, PowerPC, MIPS etc.) use the same assembly language?

Answer 28

No, each CPU has its own assembly language and some (like Intels) have several

Question 29

How many assembly language instructions does a high-level language statement (Java, C++, C, etc.) correspond to?

Answer 29

Typically more than one; high-level language statements typically require multiple assembly instructions

Question 30

Which real CPU architecture is the Y86-64 simulated CPU based on?

Answer 30

Intel X86-64

Question 31

What is Instruction Set Architecture (ISA)?

Answer 31

**The human programmer visible machine interface**. This means part of hardware which the programmer can see (such as instruction set, register, memory organization)

Question 32

What are the two major types of ISAs today?

Answer 32

RISC and CISC

Question 33

How many registers does Y86-64 have?

Answer 33

15 64-bit registers

Question 34

Why is the number of registers in Y86 unlike a real CPU?

Answer 34

Real CPUs always have a number of registers equal to a power of 2

Question 35

How many condition codes (or flags) does Y86 have, and what are they?

Answer 35

**There are 3 condition codes (or flags) and they are ZF(zero), SF(negative), OF(overflow)**.No carry flag because we are dealing with signed ints only, no unsigned overflow possible

Question 36

How are the condition codes/flags in Y86 set by the processor?

Answer 36

**Single- bit flags set by arithmetic or logical instruction**. ZF- Set if the result of the last ALU operation is 0 SF- Set if the result of last ALU operation resulted in sign bit (msb of result is 1) OF- Set if result of last ALU operation resulted in signed overflow **No C flag because Y86 CPU works only on signed numbers**

Question 37

What kinds of operands can the Y86 simulated CPU work on?

Answer 37

Signed Operands

Question 38

What sizes of operands can the Y86 simulated CPU work on? How is this different from real CPUs?

Answer 38

Only 8 bytes (64 bits). Real CPUs can work on data of different sizes 1 bytes, 2 bytes, 4 bytes, or 8 bytes.

Question 39

What size are addresses in Y86?

Answer 39

8 bytes (64 bits)

Question 40

What is the difference in the way multi-byte data is stored in memory in a big-endian versus a little-endian system?

Answer 40

Big-endian: **most significant byte of data is stored at lowest address**; **least significant byte stores at highest number address** Little-endian: **least significant byte is stored first** and **most significant byte is stored last**

Question 41

Is Y86 (and Intel) big-endian or little-endian?

Answer 41

Little-endian