Midterm 2 - Terms pg. 4-5

Question 1

ALU:

Answer 1

takes in 2 operands, an opcode, a status,

produces a result and a status

Question 2

0 = low voltage, 1 =

Answer 2

high voltage

Question 3

One wire per:

Answer 3

bit!

Question 4

Multi-bit data encoded on:

Answer 4

multi-wire buses

Question 5

Need two types of elements for stateful logic design:

Answer 5

• Combinational elements

* Sequential elements

Question 6

combinational elements:

Answer 6

• ALUs
• MUXs
• Adders
• And/or/inverter/xor gates

Question 7

sequential elements:

Answer 7

• registers w/ write control

Question 8

clocks w/ registers:

Answer 8

combination logic transforms during clock cycles

Question 9

clock cycle:

Answer 9

one full clock period (up then down)

Question 10

longest combinational delay determines :

Answer 10

clock period