Midterm 2 - Terms pg. 6-7

Question 1

pipeline:

Answer 1

state of development, preparation, or production

Question 2

analogous to laundry:

Answer 2

keep all parts of the machine operating on different parts of multiple instructions at the same time

Question 3

Pipelining MIPS - 5 Stage Pipeline:

Answer 3

IF, ID, EX, MEM, WB

Question 4

IF:

Answer 4

instruction fetch

Question 5

ID:

Answer 5

instruction decode and register read

Question 6

EX:

Answer 6

execute operation or calc address

Question 7

MEM:

Answer 7

access memory operands

Question 8

WB:

Answer 8

write back result to register

Question 9

(Equation) Performance of 5 Stage Pipeline:

Answer 9

Ideal:

time between instructions (pipelined) =
Time between instructions (non-pipe) / # of pipe stages

Question 10

speedup is due to:

Answer 10

increased throughput.

NO SPEEDUP GAIN for FIRST instruction

Question 11

Hazards:

Answer 11

situation that would prevent starting next instruction

Question 12

Structural hazard:

Answer 12

required resource is busy

can’t read from instruction memory and data memory at same time

Question 13

Data hazard:

Answer 13

need to wait for prev instruction to finish read/write

Question 14

Control hazard:

Answer 14

deciding on control action depends on prev instruction

Question 15

Memory structure hazard:

Answer 15

separate instruction/data memory OR instruction/data caches

Question 16

Forwarding/Bypassing:

Answer 16

use result when its computed

skips having to save it anywhere

Question 17

Load-Use Data hazard:

Answer 17

data not produced until 4th stage, may be needed in 3rd stage
(cannot forward/bypass)

Question 18

code scheduling:

Answer 18

removing load-use stalls by performing some other calculation between load and use.