midterm study

Question 1

the output value, Q, only changes on the rising edge of G

keeps the internal SR latch from going into an invalid state

Is a great circuit to use in a register

Answer 1

D-Flip Flop

Question 2

for an SR latch, what states are valid?

Answer 2

10
01
11

Question 3

The output value, Q, changes with the D input as long as G is high

Keeps the interal SR latch from going into an invalid state

Answer 3

D- latch

Question 4

what logic gate adds two bits together and ignores any carry

Answer 4

xor

Question 5

Using an adder, when is there a carry?

Answer 5

both input bits are 1

the sum of the input bit is 1 and the carry in is 1

Question 6

what binary number represents false?

Answer 6

0
zero

Question 7

what binary number represents true?

Answer 7

1
one

Question 8

_____ Gate: If both the inputs are high then the output is also high

Answer 8

AND

Question 9

_____ Gate: If a minimum of one input is high then the output is High

Answer 9

OR

Question 10

____ Gate: If the minimum one input is high then only the output is high

Answer 10

XOR

Question 11

______ Gate: If the minimum one input is low then the output is high

Answer 11

NAND

Question 12

____ Gate: If both the inputs are low then the output is high.

Answer 12

NOR

Question 13

The Following truth table has what outputs with an AND gate
A B
0 0
0 1
1 0
1 1

Answer 13

Output
0
0
0
1

Question 14

if one of the two inputs of an AND gate is zero (0) then the output will be ____

Answer 14

zero

Question 15

The Following truth table has what outputs with an OR gate
A B
0 0
0 1
1 0
1 1

Answer 15

Output:
0
1
1
1

Question 16

If one of two the inputs to the OR gate is 1 then the output will be _____

Answer 16

One

Question 17

In a NOR gate, the input One (1) creates an output _____ and an input of Zero (0) gives and output of _____

Answer 17

Zero
One

Question 18

The Following truth table has what outputs with an NAND gate
A B
0 0
0 1
1 0
1 1

Answer 18

Output
1
1
1
0

Question 19

The _____ gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs the operation of the AND gate followed by the operation of the NOT gate.

Answer 19

NAND

Question 20

If one or both of two inputs to the NAND gate is zero (0) then the output will be _____

Answer 20

One

Question 21

The _____ gate is a digital logic gate with n inputs and one output, that performs the operation of the OR gate followed by the NOT gate.

Answer 21

NOR

Question 22

If the inputs are both one’s then the output is 0 and if the inputs are both zero’s then the output is One other wise if a single input is one then the output is zero for what gate?

Answer 22

NOR gate

Question 23

The Following truth table has what outputs with an XOR gate
A B
0 0
0 1
1 0
1 1

Answer 23

0
1
1
0

Question 24

The _____ gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-OR. It performs based on the operation of the OR gate. . If any one of the inputs of this gate is high, then the output of the EX-OR gate will be high.

Answer 24

XOR

Question 25

If the inputs are both one's then the output is zero and if the inputs are both zero's then the output is zero, other wise if a single input is one then the output is One for what gate?

Answer 25

XOR gate

Question 26

Carry Look Ahead Input: a b c Sum: s = ______________ Propagate: p = ______________ Generate Signal: g = _________________

Answer 26

s = a ⊕ b ⊕ c p = a + b g = ab

Question 27

Carry Look ahead: - there is no ____ ____ - singal p and g do NOT depend on ___

Answer 27

carry out c

Question 28

Ripple Adder: Cin of a bit comes from the C of the ____ ____ Daisy chain multiple Full Adders

Answer 28

lower bit

Question 29

What two things cause a carry?

Answer 29

x =1 && y=1 ← generation (g) (x =1 || y=1) && Cin ← propagation (p)

Question 30

carry look ahead formula

Answer 30

g = xy p = x xor y

Question 31

there is a carry to a higher bit if:

Answer 31

Carry generated by current bit (g=1) OR There is a carry from the lower bit AND the current bit can propagate it Formula: C = g + pCin

Question 32

Carry look ahead 3 outputs:

Answer 32

g = xy p = x⊕y S = x⊕y⊕Cin Note: p and g do not depend on Cin!!

Question 33

Constructed using a circuit attached to an adder

Answer 33

Subtracting is simply adding a 2’s complement To get 2’s complement: Complement each bit Add one to the right most bit.

Question 34

Subtracter boolean equation

Answer 34

X-Y == X+(-Y) mplementing negation: XOR with 1 negates Add 1 by making Cin on the adder 1 when XORing 1

Question 35

associative property

Answer 35

A ∧ (B ∧ C) = (A ∧ B) ∧ C A ∨ (B ∨ C) = (A ∨ B) ∨ C

Question 36

Commutative property

Answer 36

A ∧ B = B ∧ A A ∨ B = B ∨ A A ∨ (B ∧ C) = (A ∨ B) ∧ C A ∧ (B ∨ C) = A ∧ (B ∨ C) A ∧ B ∧ C = C ∧ B ∧ A

Question 37

Distributive property

Answer 37

A ∨ (B ∧ C) = (A ∨ B) ∧ (A ∨ C) A ∧ (B ∨ C) = (A ∧ B) ∨ (A ∧ C)

Question 38

Identity law

Answer 38

A ∧ True = A B ∨ False = B

Question 39

Complement law

Answer 39

A ∨ A’ = True B ∧ B’ = False

Question 40

Idempotent law

Answer 40

A ∨ A = A B ∧ B = B

Question 41

double negation law

Answer 41

(A’)’ = A ((A ∧ B)’)’ = A ∧ B (same for ∨) (A ∨ B’)’ ≠ A ∨ B

Question 42

de Morgan's Law

Answer 42

(A ∧ B)’ = A’ ∨ B’ (A ∨ B)’ = A’ ∧ B’

Question 43

Absorptive law

Answer 43

A ∧ (A ∨ B) = A A ∨ (A ∧ B) = A

Question 44

Which logic gate essentially adds two bits together, albeit ignoring any carry.

Answer 44

XOR

Question 45

Using an adder, when is there a carry?

Answer 45

Both input bits are 1 The sum of the input bits is 1 and the carry in is 1

Question 46

How is the decoder like the multiplexer. How is it different? Both at the circuit level, and in the logic behind them

Answer 46

Both the decoder and the multiplexer are used to control signals. AND gates make up the inner circuits of both the decoder and multiplexer. Multiplexers often have an OR gate to output its results. There can be multiple inputs for both decoders and multiplexers, but multiplexers normally selects a singular input and decoders have a single true output line through conversion. Multiplexers are often in the form of 8:1 or 16:1 while decoders are in the form of 2:4 or 4:16. The decoder is a logic circuit with the intention of outputting 2^n lines, while the multiplexer is intended to be a selector.

Question 47

P A Ozzy Is My Dads Detective

Answer 47

Level 5- Problem-Oriented Level 4- Assembly Level 3- Operating System Level 2- Instruction Level 1- Machine Level 0- Digital logic Level -1- Device

Question 48

negative milli micros not pushy for a zoo yack

Answer 48

milli micro nano pico femto atto zepto yocto

Question 49

positive kara mara got to park e- z yeezy

Answer 49

kilo mega giga tera peta exa zetta yotta

Question 50

(D3 S1 S0) + (D2 S1 ~S0) + (D1 ~S1 S0) + (D0 ~S1 ~s0)

Answer 50

Multiplexer

Question 51

Q3 = S1 S0 E Q2 = S1 ~S0 E Q1 = ~S1 S0 E Q0 = ~S1 ~S0 E

Answer 51

Decoder

Question 52

Half Adder g = __ ___ p = ___ ____ ___ S = ____ ____ ____ ___ ____

Answer 52

X Y X xor Y X cor Y xor CIN

Question 53

full adders attached by cin and cout

Answer 53

ripple adder

Question 54

Look Ahead adder S = ___ ___ __ __ __ C = ( ____ ( __ __ ___) __ ___ ___

Answer 54

A xor B xor CIN CIN A xor B + A B