Flashcards in Module 2 Deck (18):
1
Why are RISC systems advantagous for real-time systems (3)?
Shorter instructions
-> shorter interrupt handler
-> shorter response times
2
How is programmed I/O implemented? (3)
Separate address space for I/O registers
Additional control signal to distinguish between IO and memory
Separate IN, OUT instructions needed for accessing IO registers
3
What are the advantages of programmed IO on low end and high end microcontrollers? (2)
Low end: Saves limited address space for memory components only
High end: Slower IO ports are placed in a different address space than the fast memory components, removing the need to compromise system bus speed
4
Distinguish the von Neumann architecture from the Harvard Architecture (2)
Harvard architecture has separate instruction/data buses allowing parallel instruction fecting and data load/store
5
What is the Harvard architecture popular for? (1)
Signal processors
6
What are the 5 phases of an instruction cycle?
Fetch
Decode
Load
Execute
Store
7
What are the 9 principles of CISC architecture?
1. Complex instructions take multiple clock cycles.
2. Practically any instruction can reference memory.
3. No instruction pipelining.
4. Microprogrammed control unit.
5. Large number of instructions.
6. Instructions are of variable format and length.
7. Great variety of addressing modes.
8. Single set of work registers.
9. Complexity handled by the microprogram and hardware.
8
How does polling interrupt work?
Software checks status register regularly for activity in peripheral
9
What is the tradeoff to be made with interrupt polling?
CPU utilisation factor vs. IO latency
10
What is a singe-event upset (4) and how do you mitigate it?
One or more bits are flipped in the interrupt vector
Due to electromagnetic interference in main memory, system bus or registers
causes the system to run a phantom interrupt
causing the system to crash
Give every possible interrupt vector a corresponding ISR
11
When is DMA needed?
Transferring large blocks of data efficiently
12
Describe the process for DMA (5)
An I/O device requests DMA transfer by activating a DMA - request signal (D_REQ).
This makes the DMA controller issue a bus - request signal (B_REQ) for the CPU.
The CPU finishes its present bus cycle and activates a bus - acknowledgment signal (B_ACK).
After recognizing the active B_ACK signal, the DMA controller activates a DMA - acknowledgment signal (D_
ACK), instructing the I/O device to begin data transfer.
When the transfer is completed, the DMA controller deactivates the B_REQ signal, giving buses back to the CPU.
13
What are four different types of digital signals?
Parallel, serial, wave, pulse
14
Distinguish a microprocessor from a microcontroller? (3)
Microcontrollers are newer techcnology
They are single-chip computers with memory and peripherals in their integrated circuit
whereas microprocessors use external memory and peripherals
15
In what situations are custom microcontollers developed? (3)
to save space
low-power systems
for high volume products
16
What is the downside of using custom microcontrollers? (3)
lengthy verification phase
unchangeable
unless EEPROM is used, in which case software can be changed in fixed memory space
17
What is a system-on-chip? (1)
core processor integrating non-digital components
18