MODULE 5 MIXED SIGNAL

Question 1

____ has better signal to noise ratio and higher dynamic range as compared to analog

Answer 1

Digital

Question 2

“The world is ____.”

Answer 2

analog

Question 3

For analog to be digital… it undergoes:

Answer 3

sampling (Nyquist)

Question 4

The number of bits at the output of ADC. VLSB is the smallest step that can be detected which is equal to VREF/2N for an N bit ADC

Answer 4

Resolution

Question 5

In an A/D converter, when the analog input data is quantized to a finite number of steps, ________ occurs. The maximum quantization error is VLSB/2 .

Answer 5

Quantization Error

Question 6

______ is the deviation of code transition voltage at first step from the ideal one

Answer 6

Offset error

Question 7

_____ is the deviation of the last code transition voltage from the ideal one

Answer 7

Full scale error

Question 8

Deviation of the code transition width from the ideal one (1 LSB) is called

Answer 8

differential nonlinearity (DNL).

Question 9

In an ideal ADC the code width is always one, thus, DNL is

Answer 9

zero

Question 10

is the difference between the code centers from the ideal line.

Answer 10

Integral nonlinearity (INL)

Question 11

can also be specified as the sum of DNLs.

Answer 11

Integral nonlinearity (INL)

Question 12

When a digital code at the ADC output is not produced for the corresponding input voltage, there is a

Answer 12

missing code

Question 13

Whenever there is a missing code DNL is

Answer 13

-1

Question 14

is the ratio of the input signal power over the total noise power.

Answer 14

Signal to Noise ratio (SNR)

Question 15

is defined as the ratio of the input signal to the largest peak of spur or harmonic distortion tone.

Answer 15

Spurious-Free Dynamic Range

Question 16

is the value of the input signal over the sum of the total noise and harmonic components.

Answer 16

Signal-to-Noise-and-Distortion Ratio (SINAD)

Question 17

______ is obtained from SINAD. It is commonly used instead of SINAD, since it presents SINAD in the number of bits.

Answer 17

Effective Number of Bits (ENOB)

Question 18

• better in matching as compared to a resistor string DAC
• lower power dissipation as compared to the resistor string DAC
• payoff: usually larger area than resistor string DAC

Answer 18

Charge Scaling DAC - Binary Weighted Capacitor (BWC)

Question 19

has a reduced capacitor size (layout area) than the BWC.

Answer 19

Charge Scaling DAC - Two Stage (Split) Weighted/ Capacitor Array (TWC)

Question 20

• this is an extension of the TWC array DAC
• capacitor values are largely reduced to just C and 2C
• payoff: linearity degradation due to parasitic capacitances

Answer 20

C-2C Capacitor Array DAC

Question 21

• Easily scalable to any desired number of bits
• Uses only two values of resistors which make for easy and accurate fabrication and integration
• Output impedance is equal to R, regardless of the number of bits, simplifying filtering and further analog signal processing circuit design

Answer 21

R-2R Ladder DAC

Question 22

• Easily scalable to any desired number of bits
• Uses only two values of resistors which make for easy and accurate fabrication and integration
• Output impedance is equal to R, regardless of the number of bits, simplifying filtering and further analog signal processing circuit design
• Output can exceed the reference input voltage.

Answer 22

Multiplying DAC

Question 23

• combination of a resistive and capacitive network to reduce the overall DAC area.
• less affected by parasitic impedances as compared to other DAC structures
• comparable power dissipation

Answer 23

RC-Hybrid DAC

Question 24

• relatively smaller area as compared to the other passive DAC structures
• relatively high power dissipation due to current scaling.

Answer 24

Current Steered DAC

Question 25

It consists of scaled binary capacitors, i.e., 2N-1C, 2N-2C… 2C, C, C. The last capacitor is a dummy that has equal value as the LSB capacitor. Thus, the total value of the capacitors is 2NC.

Answer 25

The Binary Weighted Capacitor Array DAC

Question 26

This has been proposed to reduce the large capacitance size in the Binary Weighted Capacitor (BWC) Array. In this approach the BWC array is divided into two smaller BWC and a coupling capacitor is added between two parts.

Answer 26

Two-Stage Weighted Capacitor Array DAC

Question 27

- Fast conversion time - High Density - Not practical for high resolution applications - Relatively high power dissipation due to usage of 2N comparators

Answer 27

Flash ADC