MPMC Flashcards
(19 cards)
Features of 8085
8 bit MP
desigined by intel in 1977
using NMOS technology
8 bit data bus
16 bit address bus, which can address upto 64kb
a 16 bit PC
a 16 bit stack pointer
six 8 bit registers arranged in pairs BC,DE,HL
Functional Units in 8085
Accumulator
ALU
GPR-there are six 8 bit GPRs BCDEHLeach register can hold 8 bit of data and they can work in pairs to hold 16 bit data BC DE HL
PC
Stack Pointer-16 bit register works like a stack which is always inc or dec by 2 duing push/pop,its 8 bit and holds temp value of ALU operations
Flag Registers-8 bit register having 5 1 bit FFs,whcih holds either 0 or 1 depending upon the result stored in accumulator(S,Z,AC,P,C)
IR and decoder-when an instruction is fetched from memory it is then stored in IR and the decoder decodes info in IR
Timing and control unit-provides timing and control signals to the mp to perform operations
Interrupt Control-controls the interrupt during a process
Serial I/O control
controls the serial data communication by using SID SOD
Adddy and data bus-unidirectional and transfers location where data is to be stored,bi directional and acrries data to be stored
Difference b/w MP and MC
MP
only consist of CPU
used in PC
uses a external bus to interface b/w RAM,ROM and other peripherals
based on Von neuman model
complicated and expensive with a large no of instructions to process
power consumption is high
eg 8085 8086 80286 80386
MC
consist of CPU Memory I/o all integrated into one chip
uses embedded system
uses an internal contrlling bus
based on harvard architecture
inexpensive and straightforward with fewer instructions to process
power comsumption is low
eg 8051
features of 8086
designed by intel in 1978
16 bit mp having 20 address line and 16 data lines that provides upto 1 mb storage
consists of powerful instruction set which provides operations like multiplication and division easily
has an instruction queue which is capable of storing six instruction bytes from the memory resulting in faster processing
it was the first 16 bit processor having 16 bit alu 16 bit registers internal databus
16 bit external databust resuling in faster faster processing
available in 3 versions
8086
8086-2
8086-1
Segmentation
Its the process in which the main memory of the computer is logically divided into different segments and each segment has its own base address
its used to enhance the speed of execution of the computer system so that the processor is able to fetch and execute the date from the memory easily and fast
Advantages of Segmentation
provides a powerful memory management mechanism
data related or stack related operations can be performed in different segments
code related operations can be done in seperate code segments
it allows to process and easily share data
allows to extend the ability of the processor
enchances the memory size of code data or stack segments
Architecture of 8086
thye internal architecture of 808 is dived into 2
1)BIU
functions
generates the 20 bit physical address for memory access
fetches instructions from memory
transfers data from the memory and i/o
maintains the 6 byte prfetch instruction queue(supports pipelining)
contains the 4 segment registers,IP,a prefetch queue and an address generation circuit
2)EU
The main components of EU are GPRs,ALU,SPRs,IR,Instructon decoder and the flag registers
1)fetches instruction from the queue in BIU,decodes and executes arithmetic and logic operations using the ALU
2)sends control signals for internal datatransffer operations within the mp
3)sends request signals to the BIU to access the external module
4)operates with respect to T states and not machine cycles
Instruction Pointer(8086)
16 bit register that holds the offset of the next instruciton in the code segment
ip is incremented after every instruction byte is fetched
ip gets a new value whenever a branch instruction occurs
CS is multiplies by 10H to give the 20 bit physical address of the code segment
Segment registers(8086)
CSR
holds the base adress for the code segment.All programs are stored in CS and accessed via IP
DSR
holds the base address of DS
SSR
holds the base address of SS
ESR
ES holds the base address of ES
Address Generation Circuit(8086)
BIU has a physciall address generation circuit
generate the 20 bit physical address using segment and offset addressses using the formula
physical address=segment address*10h+offset address
6 byte pre fetch queue(8086)
its 6 byte queue(FIFO)
fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining
gets flushed whenever a branch instruction occurs
16 bit GPrs(8086)
has 4 Gprs
AX,BX,CX,DX.They store intermediate valuyes during execution ,each of these have 2 8 bit parts
Ax-holds operands and sesults duiring multiplication and division operations also an accumulator during string operations
BX-holds the memory address(offset adress) in indirect addressing modes
CX-golds count for instructions like loop,rotate,shift and string operations
DX-used with Ax to hold 32 bit values during multiplication and division
16 bit SPRs(8086)
Stack pointer
Points to the top of the stack,used during instructions like PUSH POP CALL RET
Base Pointer
holds offset address of any location in the stack segment,used to access rendom locations of the stack
Source Index
holds offset address in DS during STring operation
Destiation Index
holds offset adress in ES during String operation
16 bit long FLAG register
6 status- Carry,Parrity,Auxilary carry,Zero,OF,Sign
3 Control flags- Trap,interrupt,direction
Physical Memory Organisation
provides 20 bit adress to memory which locates the byte being referenced
uses the concept of segmented memory,to address a memory capacity of 1 mb and its byte is organized
1mb memory is divided into 16 logical segments.each segment contains 64kb of memory
memory is organized in linear array of upto 1 million bytes(00000-FFFFF)
memory is logically dived into code,data,extra data,and stack sements of upto 64k bytes each
its organized into odd memory bank(D8-D15) and even memory bank(D0-D7)
the processor provides two enable signals A0 and BHE
Features in 8051
introduced in 1981
8 bit MC
128 bytes of RAM
4k bytes of on-chip ROM
two timers(16)
one serial port
four I/O ports,each 8 bit wide so total 32 pins
5 interrupt sources
Architecture of 8051
8 bit CPU with 2 registers (A(accumulator) and B)
internal ROM of 4k bytes
internal RAM of 128 bytes
its again divded into 4 banks with 8 registers(R0-R7) in each bank,(00-1F)
16 bit addressable area(20-2F)
80 Genral purpose area(30-7F)
16 bit pc and DPTR(pc starts at 0000h)
two 16 bit timers T0 and T1
control registers
Serial Data transmitter and revciver for full-duplex operation
Interrupts Two external and three internal
Oscilator and clock circuit
32 I/0 pints arranged as 4 ports
8 bit Stack pointer and processor status word
Osculator(8051)
mc is a device that needs clock pulses for its operation of mc applications
for this purpose microcontroller 8051 has an on chip oscillatorwhich works as a clock source for CPU of the MC
The output pulses of oscilator are stable. therefore it enables synchronized work of all parts of 8051
R Registers(8051)
set of 8 registers namely R0-R7 ,these function as auxilary or temporary storage registers in many operations
B register(8051)
similar to the accumulator in the sense it may old an 8 bit value,the b register is used by only 2 8051 instructions mul AB and DIV AB
aside from that its often used as yet another temporaty storage register,much like a 9th register
DPTR
its the 8051’s only user accessible 16 bit register
used for pointing to data
used by the 8051 to access external memory using address indicated by DPTR
RAM(8051)
there are 128 bytes of ram
assigned addresses 00 to 7f
the 128 bytes are divided into three different groups
1)a total of 32 bytes from 00-1F hex are set aside for register banks and the stack
2)a total of 16 bytes from 20H to 2FH are set aside for 16 bit addressable read/write memory
3)total of 80 bytes from 30H to 7FH are used to read and write storage called scrath pad
Special Registers in 8051
The higer 128 bytes of RAM 80 to FFH consists of special function registers,using this we can control different peripherals like timers,serial port all i/o ports etc
pin diagram(8051)
1-8 (port1) is used for simple I/O operations and these ports work as bidirectional port,meaning that all the pins of port 1 work as a input pin or output pins
1 in i/o port = input pin and vice versa
9-reset input pin,which is used to reset the 8051 to its inital value (logic 1)
10-17(port3)
10-used as RXD
11-used as TXD
12 and 13-used for external harware interrupt 0 and 1
14 and 15 -used for timer 0 and timer 1 external input
16-used for external memory write
17-used for external memory read
18-19-XTAL2 and 1 used for interfacing external oscilator
20-GND
21-28(port2)-its a bidirectional i/o port,all pins of port 2 work as a input pin or as a output pins (only when we dont use any external memory)
29-PSEN used to enable external program memory and read a signal from the external program memory
30-address latch enable pin,used to enable or diable the external memory interfacing
31-EA pin this pin allows external program memory
32-39(port0)-used as bidirectional pin like port 2 ,but when ale pin 1 then this is used as databus,0 this port is used as lower order address bus(a0-a7)
40-VCC
Addressing Mode(8051)
various ways of accessing data is known as addressing modes
1)immediate
2)register
3)direct
4)register indirect
5)indexed
1)the data is provided in the instruction itself,the data is provided immediately after the opcode
MOV A,#25
# is used for immediate data
2)one of the 8 registers R0-R7 is specified as operand in the instruction
MOV A,R0
movment of data between two R registers are not allowed
3)the source or destination address is specified by using 8 bit data in the instruction ,only internal data memory can be used
MOV R0,40h
MOV 56,A
4)in this mode the source or destination address is given in the register,by using register indirect addressing mode the internal or external addresses can be accessed
R0-R1 are used for 8 bit address and DPTR for 16 bit addresses no other register can be used for addressing purpose
MOV A,@R0 ; move contents of RAM location whose address :mov r0,#45h
5)in the indexed addressing mode the data in the program memory can be accessed,the destination operand is always A
MOVC A,@A+PC;C refers to code byte if a holds 30H and pc is 1125H the contents of progream memory location is 1155H which is moved to A
8 bit add/sub(8051)
8000 MOV DPTR,#8500
8003 MOVX,@DPTR
8004 MOV R0,A
8005 INC DPTR
8006 MOVX A,@DPTR
8007 MOV R1,A
8008 INC DPTR
8009 ADD/SUB A,R0
800A MOV @DPTR,A
800B SJMP
8 bit mul/div(8051)
8000 MOV DPTR,#8500
8003 MOVX,@DPTR
MOV F0,A
INC DPTR
MOVX A,@DPTR
INC DPTR
MUL/DIV AB
MOV @DPTR,A
SJMP
16 bit add
8000 MOV DPTR,#8500
8003 MOVX,@DPTR
8004 MOV R0,A
8005 INC DPTR
8006 MOVX A,@DPTR
8007 ADD A,R0
8008 INC DPTR
8009 MOVX @DPTR,A
INC DPTR
MOV A,#00
ADDC A,#00
MOVX @DPTR,A
SJMP
16 bit sub
8000 MOV DPTR,#8500
8003 MOVX,@DPTR
8004 MOV R0,A
8005 INC DPTR
CLR C
8006 MOVX A,@DPTR
8007 SUBB A,R0
8008 INC DPTR
8009 MOVX @DPTR,A
INC DPTR
MOV A,#00
ADDC A,#00
MOVX @DPTR,A
SJMP
16 bit Mul/DIV
8000 MOV DPTR,#8500
8003 MOVX,@DPTR
8004 MOV B,A
8005 INC DPTR
8006 MOVX A,@DPTR
8007 DIV AB
8008 INC DPTR
8009 MOVX @DPTR,A
INC DPTR
MOV A,B
MOVX @DPTR,A
SJMP
pin diagram 8086
1- GND
16-2 - AD0 - AD14
17-NMI
18-INTR
19-CLK
20-GND
21-RESET
22-Ready
23-TEST
24-INTA qs1
25-ALE qs0
26-DEN s0
27-DT/R s1
28-M/IO s2
29-WR
30-HLDA
31-HOLD
32-RD
33-MN/MX
34-BHE/S7
35 - 38 - ad19(s6) - ad16(s3)
39-ad15
40 - vcc
