paper 1

Question 1

Fetch stage of the FDE cycle

Answer 1

• value of PC copied to MAR
• PC ticks over to next address
• MAR address cent to RAM via address bus and copy instruction sent from CU via Control unit
• Instruction copied to MDR via Data bus
• MDR copied to CIR

Question 2

Decode stage

Answer 2

• content of CIR split into Opcode and Operand
• Opcode matched with instruction in instruction set
• if Operand not immediate the value of the address is fetched

Question 3

Execute

Answer 3

Opcode executed on operand

Question 4

Execute

Answer 4

Opcode executed on operand

Question 5

pipelining

Answer 5

three separate instructions processed simultaneously, instruction one executed while instruction two is being decoded and instruction three is being fetched - reduces CPU idle time - can be broken down further to reduce idle time more

if predicts wrong branch the pipe must be flushed and benefits are lost as correct instruction is loaded

Question 6

von neumann

Answer 6

original computer architecture has single CU, ALU, registers and memory units - memory shared by instructions and data as are the buses - uses stored program concept

Question 7

harvard architecture

Answer 7

uses two memory storage units one for data and another for instructions, two copies of buses - more efficient, data and instructions fetched at the same time common in embedded system

Question 8

contemporary architecture

Answer 8

combines Harvard and von neumann, main memory remains in von neumann format while cache is dived like with a Harvard system

Question 9

CISC

Answer 9

systems using a larger instruction set (80-100), each instruction can be more complex so may take several clock cycles to complete one instruction.
+ easier to translate from high level to machine code
+ less ram required for less lines of code
+ specialized instructions used rarely
- larger due to increased storage for more instructions and more cooling required for increased power consumption
- decreased clock speed
- may require several clock cycles per instruction
-

Question 10

RISC

Answer 10

a smaller instruction set (30-40) more simplistic - 1 instruction = 1 clock cycle
+ high level languages compiled to more efficient code
+ 1 clock cycle per instruction
+ smaller - reduced power and storage
+ decoding instructions more simple
+ cheaper - less components
- performance depends on skill of programmer
- longer compile time and longer machine code
- more effort for programmers

Question 11

scheduling

Answer 11

function of operating system dividing CPU time between jobs - can be done pre-emptivly (stopping jobs during execution to giver others processor time) or non pre-emptivly (once a job is started it is not stopped until completed)

• round robin - pre-emptive - each job given a set amount of time, first come first serve, after time used it is moved to the back of the queue if not complete + all jobs seen to - inefficient split meaning all jobs take a long time - does not account for priority
• First come first server - non pre-emtive - as jobs arrive they are processed to completion + strait forward to implement - vulnerable to malware if loaded before AV - does not account for priority
• shortest job first - non pre-emptive - jobs are ordered in ascending order in terms of length, suited to batch systems to reduce wait time - can starve longer processes - requires processor power to calculate job length +completes lots of jobs quickly
• shortest time remaining - the fastest job to be completed at a given point in time is seen to first - can starve longer processes - requires processing power to calculate queue
• Multilevel feed back queue - divides schedule into multiple queue’s depending on the priority of tasks - only once top queue is empty to is the next queue seen to - another scheduling algorithm is implemented on each level - requires extra processing power - inherits pros and cons of algorithm used at each level + takes into account priority

Question 12

translators

Answer 12

a program which converts high level code to machine code

Question 13

compiler

Answer 13

translates all code in one go, carries out all checks and reports errors before execution - whole program must be recompiled if change is made - compiled code is specific to the processor and operating system it is compiled on - can be ran without a translator present - creates executable separate to source code

Question 14

interpreter

Answer 14

translates code line by line during execution - stop and produce error when found - slower as code is translated each time it is ran - useful for testing and debugging - interpreter required to run - more portable

Question 15

assembler

Answer 15

translates assembly to machine code - platform specific - instructions dependent on specific processor - 1 assembly line = 1 machine line

Question 16

stages of compilation

Answer 16

lexical analysis - white space and comments removed - key words variables and constants replaced with tokens, tokens stored in symbol table
syntax analysis - tokens are analyzed against rules of program - tokens that break the rules are flagged as syntax errors - an abstract syntax tree is produced representing source code - semantic analysis also spots logic errors
code generation - abstract syntax tree used to produce machine code
optimization - code optimized, adds time to translation but decreases execution time - excessive optimization can lead to behavioral changes

Question 17

assembly language

Answer 17

very low level code (one up form machine code) - it is its own family of code - translated using an assembler - uses mnemonics rather than binary - non portable - allows for direct interaction with registers - used in embedded systems

Question 18

little man computer mnemonics

Answer 18

ADD - Add the value at the given memory address to the value in the Accumulator
SUB - Subtract the value at the given memory address from the value in the Accumulator
STA - Store the value in the Accumulator at the given memory address
LDA - Load the value at the given memory address into the Accumulator
INP - Allows the user to input a value which will be held in the Accumulator
OUT - Prints the value currently held in the Accumulator
HLT - Stops the program at that line, preventing the rest of the code from executing.
DAT - Creates a flag with a label at which data is stored.
BRZ - Branch if zero - Branches to a given address if the value in the Accumulator is zero. This is a conditional branch.
BRP - Branch if positive - Branches to a given address if the value in the Accumulator is positive. This is a conditional branch.
BRA - Branch always - Branches to a given address no matter the value in the Accumulator. This is an unconditional branch.

Question 19

Structured Query Language

Answer 19

declarative language used to manipulate databases - enables creating, removing and updating
SELECT collects data from a given field
FROM specifies a table to operate on
WHERE specifies operation criteria
ORDER BY orders field in Ascending or Descending order
JOIN combines multiple records from multiple tables on a common filed
CREATE makes a new database, must specify fields, PK data type and if it must be filled
ALTER add delete or modify columns
INSERT INTO inserts a new record
UPDATE updates a record
DELETE removes a record

Question 20

referential integrity

Answer 20

ensuring consistency in a DB - ensures data is not removed if required elsewhere etc

Question 21

transaction

Answer 21

a transaction is a single operation executed on data, a collection of operations can also be described as a transaction

Question 22

ACID

Answer 22

Atomicity - A transaction should be processed in its entirety else not at all

Consistency - referential integrity rules must be maintained between liked tables

Isolation - simultaneous execution of transactions should lead to the same result as if they were executed consecutively

Durability - once executed a transaction will remain so regardless of circumstance ie powercuts

Question 23

record locking

Answer 23

to prevent simultaneous access a record is locked to prevent inconsistency whilst a transaction is being processed

deadlock - where a record is locked by one process as it try’s to access another which is locked by another process trying to access the original record

Question 24

redundancy

Answer 24

having multiple copies of valuable data in different physical locations - if one is damaged the others can be accessed to recover it

Question 25

internet structure

Answer 25

a network of networks which allows computers to communicate - continents are linked with large backbone cables underwater

Question 26

TCP/IP stack

Answer 26

Transfer Control Protocol / Internet Protocol - a group of protocols governing how computers communicate
Application layer - specifies which protocol is used in relation to the application - HTTP POP3 FTP TLS/SSL
Transport - uses TCP to establish end-to-end connection between source and recipient - splits data into packets with numbers, total number of packets, and port number
Network layer - adds source + destination IP - where routers operate
Link Layer - Adds MAC addresses

once received header and footer info is stripped in reverse order

Question 27

ASCII

Answer 27

American Standard Code for Information Interchange, each character represented by a 7 bit (128 different combinations) binary - A-Z = 65-90, a-z = 97-122 + codes for numbers and symbols - not enough characters for foreign alphabets

Question 28

extended ASCII

Answer 28

a patch for 7bit ASCII extending it to 8bit, doubling the number of potential binary strings

Question 29

unicode

Answer 29

varying number of bits from 8-32 allows for all known languages and emojis with left over characters

Question 30

floating point binary

Answer 30

two parts, mantissa and exponent - mantissa is the actual value and the exponent is how many places the decimal point moves, positive moves to right, negative to left
all floating point binary’s in 2’s a compliment form, normalized when starts 01 or 10