Part 1 Flashcards
(40 cards)
Why does it matter how many bits you use for a given data type?
arithmetic operations on larger bits of data (i.e. 32 bit) generate more heat than say 8 bit data
How many numbers can be stored in an unsigned 8 bit representation AND from which number until which one.
- From 0 to 255
What is wrong with sign-magnitude representation?
It wastes one number in 0 and -0 and allows only a range from -127 unitl 127. Only 255 numbers
How does 2s complement representation work?
It’s an alternative to sign-magnitude and it works by changing the value of the MBS from positive to negative
What are the benefits of 2s complement?
It allows a range of 256 numbers and the circuitry for addition is the same as for subtraction- -128 to 127
What is a disadvantage of 2s complement
When you are subtracting a smaller number from a larger number you get a lot of negative numbers which translates into a lot of bit flips generating a lot of heat
What’s wrong with floating point numbers?
Precision: Dividing a very large number by a very small one might result in an inaccurate output
What is the definition of a proposition?
We can tell whether statement is true or false and it’s unambiguous. “It is true that”
What is the complement of: e = x or y or z
(not)e = (not)x and (not)y and (not)z
Minterms and maxterms. Where do they appear? and what are they equivalent to?
Minterms are products and appear in DNF. Maxterms are sums and appear in CNF
What is the difference between a PMOS and a NMOS transistor?
PMOS is initially closed and allows current to flow. It opens when applied 1. NMOS is initially open and closes when applied a 1
In an inverter, which transistor is open and which is closed when A is set to VDD
NMOS (0) transistor is closed setting Q to VSS and PMOS is open (1)
What logic gates are used for the sum and carry outputs in an adder respectively?
sum: xor
carry: and
When is XOR defined to be true for multiple arguments?
If and only if an odd number of args is true (a XOR b XOR c)
What is the (negative) implication of implementing a ripple-carry adder?
You have to wait for the signal to propagate to know the value of higher order bits
Why do we need log2(N) number of select bits when N = number of signals to select from?
Because N represents the number of select signals we have and we need the appropriate number of bits to represent that amount of singals. I.e to represent 8 (select signals) we need 3 bits (which can represent up to 8 combinations)
What is the difference between a multiplexor and a demultiplexor?
A multiplexor selects which input signal to propagate whereas a demultiplexor selects into which output signal to propagate the (single) input signal
What is a ring oscillator?
Device composed of an odd number of inverters chained together. The output of the chain is made as an input to the start of the chain and the output oscillates between 2 voltage levels
What does setting and resetting the latch mean in an SR latch?
Setting means activating S and resetting means activating R. Since the input singals are active low this means that S is activated when made 0 and R the same
Which is the “not allowed” output in an SR latch and why is it not allowed?
When both inputs equal 0. It is not allowed because in this scenario both outputs would be equal to each other (1) which defeats the point of an SR latch. Q and Q’ are supposed to be inverted.
How does a D latch work and what is its benefit over the SR latch?
It has 2 inputs. 1 single data input and a enable/disable (propagation) input which when set to 0 disables propagation and stores data value. The benefit it has is that it eliminates the”DE” part of the latch eliminates possibility of a “0 0” input on the SR part of the latch (which is an SR latch itself) which is the “not allowed” value
What is “level sensitive” and “edge sensitive” and what are examples of devices that implement these concepts?
Level sensitiveness happens when a singal can be propagated when the clock singal is “on” or 1. An example of this are latches (i.e. D latch). Edge sensitiveness happens when a singal is propagated when the clock signal rises from 0 to 1 (but not WHILE it is 1). An example of this are flip flops (i.e. JK flip flops)
What are timing cosntraints used for?
When a data singal changes, there’s a small period of time when we don’t know what is its value so timing cosntraints are used to avoid unexpected behaviour. A setup time and hold time are set to define how long before the event (clock edge) and after the event the singal should be settled
Why does the second latch in a master slave flip flop need to have the enabler inverted?
The inverter prevents the data value from being propagated unless initial enabler value is 0 (which would be 1 in second D latch) enabling the data value to reach the second input and simulate only changing when falling. Basically prevents racing and replaces it with toggling