Processor Types and Instruction Sets

Question 1

Execution pipeline is a ____ optimization technique.

It allows ___ in ___.

Answer 1

Hardware; execution of instructions; parallel

Question 2

Execution pipeline are used by ___ architectures.

RISC/CISC?

Answer 2

RISC

Question 3

Which of the following about execution pipeline is false?
A. Each stage operates in parallel with a different instruction
B. An N stage pipeline operates over N instructions simultaneously
C. Each stage takes one clock cycle
D. Each instruction takes one clock cycle regardless if the pipeline is full or not

Answer 3

D.

Each instruction takes one clock cycle once the pipeline is full

Question 4

Which of the following about pipeline control is false?
A. The pipeline requires programmers intervention
B. The programmer can write code that can “stall” the pipeline
C. Pipe stall happens when the next instruction depends on the result of the previous instruction

Answer 4

A.

The pipeline is executed by the processor without the programmers intervention

Question 5

Reasons of a pipe stall:-

1. Access to ___
2. Call an ___ that takes long time eg. FP arithmetic
3. Branch to ___
4. Call a ___

Answer 5

RAM; instruction; new location; function

Question 6

To minimize stalls:-
Avoid introducing ___
Delay references to ___

Answer 6

unnecessary branches;

result registers