Questions Flashcards
“Design a 4 to 1 multiplexor…”
Sequential vs Combinational
Whats the difference between a latch and a flip-flop?
What do you need to remember about solving this question?
In this case, you need to first write out the boolean equation.
From that you can create the 3 input bits, since its a 4:1 multiplexor there will be one extra input bit equal to 0.
Essentially, if the
What is the simplified boolean expression of this?
A
Can this be simplified?
If you need to implement a certain function in a 4 to 1 multiplexor, what are the steps you need to take?
Determine the truth table of your function and from there the minterms.
The data inputs must be chosen to select the required minterms.
Any input terms that are left need to be set to 0.
Implement an EXCLUSIVE OR function in a 4 to 1 multiplexer. Reprogram the multiplexer to perform the AND function.
How do you solve this?
Briefly describe the physical operation of N-type MOS transistor?
‘MOS’ stands for metal-oxide-semiconductor; the MOS device is like a sandwich made of these three types of material. A cross-section through an N-MOS transistor is shown below:
Assume first that gate, drain and source are at approximately same potential. Since there are effectively two diodes back-to-back (N-P and P-N) between the source and drain then no current can flow because one of the diodes will always be reverse biased; the device acts as an open-circuit between S and D.
When a positive voltage is applied to the gate which is above the threshold voltage of the device (typically +0.5V), the effect is to produce a field through the oxide layer which attracts electrons from the source and drain contacts to form a layer of electrons under the gate. This layer of electrons allows current to flow in either direction between drain and source; the device is now conductive and acts approximately as a short-circuit between S and D.
Describe the disadvantages, in terms of the power consumption and switching speed, of the switch-resistor logic circuit implementation described in part (b), compared to a switch- switch logic circuit.
[4 marks]
“Switch resistor circuits have a serious problem of an uncomfortable trade-off between power consumption and switching speed. To take the circuits using N-type MOS transistors for example, the pull-up of the output voltage from 0V to 5V is performed by the resistor, but the output is driving into other gates which have input capacitance and in order to get a rapid change (fast switching speed) the resistor value needs to be small (small time constant = RC).
When the output voltage changes form 5V to 0V, the switches provide the pull-down and effectively connect the resistor between the 5V and 0V power supply rails. The adoption of a small resistor value to get fast switching speed in the pull-up phase now causes high power supply current drain in the pull-down phase. Hence, fast processing speed and low power consumption cannot be obtained simultaneously.
Similar comments apply to the circuits using P-type MOS transistors but the phases are reversed. This problem can be solved by eliminating the resistor and using a combination of N-type and P-type MOS transistors in a single circuit, in the form of switch-switch logic circuits.”
So basically, the pull up of the output voltage from 0v to 5v is done by the resistor. In order to get a rapid change(fast switching speeds), resistor value needs to be small. When the output voltage changes from 5V to 0V, the switches provide the pull down, the small resistor value now causes a large power supply current drain. Thus, fast switching speeds and low power consumption cannot be possible with switch resistor circuits. Switch-switch logic elimates the resistor and the problem, it is a combination between n-type and p-type MOS.
How do you convert this N-type switch-resistor circuit to switch-switch?
Discuss the following practical problems in the physical implementation of digital circuits…
i) The wires and leads interconnecting logic components in a system will have a small but finite inductance. When a logic gate switches, a short pulse of current flows in the power supply lines. A changing current in an inductor will generate a voltage v = L di/dt. The voltage spike can cause serious malfunction and damage in logic circuits.
The induced voltage can be removed by attaching small radio frequency capacitors between the supply input and earth pins of each logic circuit. The capacitors decouple the power supply and effectively short out the high-frequency current pulses.
ii) Crosstalk can occur when signals running along adjacent tracks or wires are coupled together by mutual capacitance. Cross-talk can be eliminated by modifying the layout of the circuit board, increasing the spacing between tracks or separating cross-talking tracks with a third track at ground potential. In extreme cases, a ground plane may be needed. If cross-talk occurs between wires, a twisted pair of wires with one at ground potential may afford adequate isolation. In extreme cases screened cable must be used.
Question regarding hazards in practical combinational logic circuits.
Answer: Practical electronic logic circuits are not ideal devices.
They have a finite time to operate.
This can introduce delays into the propagation of information.
In these sorts of questions, it is best to just use F=A.A_bar
When sketching timing waveforms you have to show how the input X stays at 1 for a while since the inverter has not had enough time to change the value, and thus temporarily the input into the AND gate is 1.1, so it outputs 1, which is not the desired output.
Identify whether hazards exist in the following function:
In this case because C.D does not intersect with the other loops, there is a hazard.
It is key to understand that separate loops produce an output of 1 to the overarching OR gate through separate AND gates. The OR is designed requires both AND gates to output the correct value simultaneously. If this is not done, a false 0 could be produced.
In this case, the loops with inverted variables switch later than the C.D loop, because of the extra step of the inverter, which takes a finite amount of time. Hence for a brief instant, there could be a false output.
Figure 13.1 shows the implementation of a Finite State Machine (FSM). The 2-bit register,which operates as the FSM’s memory, consists of two D-type flip-flops in parallel. The design of the combinational logic block in the FSM is shown in Figure 13.2.
a) State whether the circuit is implementing a Mealy machine, or a Moore machine, giving the reason for your answer.
The circuit is implementing a Moore machine, since the output is dependent only on the present state, and not on the present input.
Design a cellular logic circuit (i.e. a circuit comprising a number of cascaded identical logic blocks) which inputs an N bit binary code and outputs a logical 0 if there are an even number of logical 1’s in the input, and outputs a logical 1 otherwise.
[5 marks]
Final circuit is EXOR gates in series feeding each other.
A simple state diagram is shown in Figure 6.1. Define and explain the purpose of each element in the state diagram.
Input: Specifies the input condition that cases the associated transition
State: The possible states that the FSM machine can be in
Transition: Describes which state the machine goes to under each input condition
Action: Specifies the action that is to be executed when the transition occurs
Activity: Specifies the activity that is to be executed when in a particular state.
What is the activity of a FSM ?
The second 0
What is the action of a FSM?
The 0 on the outside
JK flip-flop question
