Revision day two - logic design, single cycle, multi cycle, MIPS and C Flashcards

1
Q

Data path

A

performs the data operations as commanded by the program instructions

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2
Q

control

A

controls the data path, memory and I/O according to program instructions

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3
Q

disadvantages of single cycle

A

speed - the cycle time is the Time for the most complex instruction but the average instruction needs less time

cost - functional units cannot be resused within one instructions execution

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4
Q

execution time

A

instruction count x number of cycles per instruction x cycle time

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5
Q

fetch step

A

instruction is fetched from memory
increment pc to the next instruction (pc +4)

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6
Q

instruction decode

A

retrieve the appropriate values from register files
decode the instruction
create control signals that will accompany the execution
calculate the target address - sign extend the immediate, shift left by 2 (word align) and add to (pc +4)

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7
Q

R-format instruction

A
  1. perform arithmetic and store output in ALUOut
  2. write result to correct register
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8
Q

Store instruction

A
  1. calculate address - 16 bit offset (sign extended) + first register source operand
  2. write to memory
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9
Q

Branch instructions

A
  1. compare operands using ALU subtraction

if 0 - address target is changed to one calculated in step two

else pc register will remain at PC+4

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10
Q

RISC

A

reduced instruction set computer

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11
Q

CISC

A

complex instruction set computer

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12
Q

instruction set architecture

A

the language of the computer

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13
Q

features of CISC

A

very few registers
very little memory

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14
Q

features of RISC

A

more memory + faster clock frequency
fixed length and fixed format instructions (for easy, fast decoding)

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15
Q

big endian

A

the msbyte of the data is placed at the location with the lowest address

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16
Q

little endian

A

the least significant byte of the data is placed at the byte with the lowest address

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17
Q

how can a word be stored in memory

A
  1. unaligned - placed anywhere
  2. aligned - at an address which is a multiple of the word size
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18
Q

memory regions and management in c

A

heap - dynamically allocated memory (managed by the programmer)
stack - for function / method calls (managed by compiler)
static - for data that lives during the whole lifetime of the program (initialised when the process starts

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19
Q

extern

A

extends the scope before the definition and to other files

20
Q

static

A

lets it hide from other files

21
Q

what does xor instruction do

A

inverts the bits

22
Q

in a processor with caches, an index is used to

A

locate the data in a direct mapped cache

23
Q

data representation affects what two things

A

circuit complexity
circuit speed

24
Q

name one thing that will not trigger a processor exception

A

cache miss

25
combinational logic
logical system whose blocks do NOT contain memory computes some output given some input
26
sequential logic
logical system whose blocks contain memory hence the output depends on the input and current values in the memory
27
three ways all logical circuits can be built
and, or, not nand nor
28
decoder
a logic block that has n-bits input and 2^n bits output where each output is asserted for each input combination
29
multiplexer (MUX)
output is one of the inputs selected by a controller
30
what does a multiplexer consist of
1. detector that generates n different input values 2. array of n AND gates 3. one OR gate (that combines the output of the AND gates)
31
32-bit adder
a circuit made by connecting 32 adders
32
propagation delay
time between input signal change and output signal change at the other end
33
three things that the propagation delay depends on
1. technology 2. delay through each gate 3. number of gates driven by gates output
34
asynchronous
state of circuit changes whenever input changes (there is no clock)
35
synchrouous
state can only change at times synchronised to an external signal (or clock)
36
edge triggered clock
clock scheme in which all changes occur on the clock edge
37
D flip flop
a memory element for which an output is equal to the value of the stored state inside the element for which the internal state is changed only on the clocks edge
38
D latch
A memory element for which an output is equal to the value of the stored state inside the element for which the internal state changes whenever the appropriate input changes and clock is asserted
39
setup time
the minimum time that the input to the memory device must be valid before the clock edge
40
hold time
a minimum time during which the input must be valid after a clock edge
41
Two details of the FSM
synchronised, every change happens in a clock cycle sequential logic can be described via a FSM
42
glitch
when different inputs have different delays
43
Moores law
the number of transistors doubles every 18 - 24 months. at the same time the cost of the transistor reduces
44
compiler
a program that translates a high level language (C, java) into aa sequence of assembly language statements
45
assembly language
a symbolic representation of machine instructions
46
operating system
a supervising program that manages all programs in a computer such as 1. basic I/O interaction 2. allocation and memory 3. protection of sharing the computer
47
load instruction
3. calculate address - 16 bit offset (sign extended) + first register source operand 4. read from memory 5. store in destination register