RISC Flashcards
What does RISC mean?
Reduced instruction set computer
How do RISC’s aim to increase performance?
Moving less frequently required hardware operations into software
Reducing hardware cost/complexity
Reducing critical path delay, increased clock speeds
Advantages of simpler instructions?
Hard wired decoding - Less complexity of instructions - Less instructions No need for rom/functional units Instruction decode faster
Disadvantage of using moving away from hardware complex instructions?
Each instruction does less, so more instructions / memory requirements.
What is pipelining?
Splitting up instructions into multiple stages and allowing them to run simultaneously
Fetch decode execute happen in parallel.
How does pipelining affect latency & throughout?
Latency doesn’t improve
Throughout does.
What is the processing speed up of pipelining related to?
How many stages (e.g. how many instructions at a time)
How does RISC improve performance?
Reducing the critical path delay
(Fastest clock speed)
Keeping the pipeline full! No multi cycle instructions in RISC!
How does RISC cope with multi cycle memory reads? (Address to bus/read memory array/data to bus/read bus)
Most instructions can’t do memory reads/writes (only Load/Store can do multiple cycles, where they stall the pipeline till the data has been accessed)
Why do RISC have so many registers?
Use them instead of slow memory to reduce stalls to pipeline (more full)
